From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 941 invoked by alias); 4 Aug 2015 12:34:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 928 invoked by uid 89); 4 Aug 2015 12:34:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-io0-f175.google.com Received: from mail-io0-f175.google.com (HELO mail-io0-f175.google.com) (209.85.223.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 04 Aug 2015 12:34:11 +0000 Received: by ioeg141 with SMTP id g141so14972122ioe.3 for ; Tue, 04 Aug 2015 05:34:09 -0700 (PDT) X-Received: by 10.107.151.75 with SMTP id z72mr2973436iod.46.1438691649593; Tue, 04 Aug 2015 05:34:09 -0700 (PDT) Received: from msticlxl57.ims.intel.com (fmdmzpr04-ext.fm.intel.com. [192.55.55.39]) by smtp.gmail.com with ESMTPSA id qs10sm933949igb.14.2015.08.04.05.34.08 (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 04 Aug 2015 05:34:09 -0700 (PDT) Date: Tue, 04 Aug 2015 12:34:00 -0000 From: Kirill Yukhin To: Uros Bizjak Cc: GCC Patches Subject: Re: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl. Message-ID: <20150804123401.GE32256@msticlxl57.ims.intel.com> References: <20150804114734.GA32256@msticlxl57.ims.intel.com> <20150804123126.GC32256@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150804123126.GC32256@msticlxl57.ims.intel.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2015-08/txt/msg00178.txt.bz2 On 04 Aug 15:31, Kirill Yukhin wrote: > On 04 Aug 14:10, Uros Bizjak wrote: > > On Tue, Aug 4, 2015 at 1:47 PM, Kirill Yukhin wrote: > > > Hello, > > > - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*") > > > - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig") > > > - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")]) > > > + (set_attr "prefix_data16" "*,*,*,*,*,1,*,*,*,*") > > > > Please change the above to: > > > > (set (attr "prefix_data16") > > (if_then_else (eq_attr "alternative" "5") > > (const_string "1") > > (const_string "*"))) > Thanks, fixed! > > > > Uros. Wrong patch. Here is proper. commit 1055739cb51648794a01afd85f59efadd14378ed Author: Kirill Yukhin Date: Mon Aug 3 15:21:06 2015 +0300 Fix vec_concatv2df and vec_dupv2df to block wrongly enabled AVX-512VL insns. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 5c5c1fc..9ffe9aa 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -784,7 +784,8 @@ (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64, sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, - fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq" + fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq, + avx512vl,noavx512vl" (const_string "base")) (define_attr "enabled" "" @@ -819,6 +820,8 @@ (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW") (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ") (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ") + (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL") + (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL") ] (const_int 1))) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0970f0e..ca1ec2e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -8638,44 +8638,50 @@ (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) (define_insn "vec_dupv2df" - [(set (match_operand:V2DF 0 "register_operand" "=x,v") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") (vec_duplicate:V2DF - (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))] + (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))] "TARGET_SSE2 && " "@ unpcklpd\t%0, %0 - %vmovddup\t{%1, %0|%0, %1}" - [(set_attr "isa" "noavx,sse3") + %vmovddup\t{%1, %0|%0, %1} + vmovddup\t{%1, %0|%0, %1}" + [(set_attr "isa" "noavx,sse3,avx512vl") (set_attr "type" "sselog1") - (set_attr "prefix" "orig,maybe_vex") - (set_attr "mode" "V2DF,DF")]) + (set_attr "prefix" "orig,maybe_vex,evex") + (set_attr "mode" "V2DF,DF,DF")]) (define_insn "*vec_concatv2df" - [(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x") (vec_concat:V2DF - (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0") - (match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))] + (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0") + (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))] "TARGET_SSE && (!(MEM_P (operands[1]) && MEM_P (operands[2])) || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))" "@ unpcklpd\t{%2, %0|%0, %2} vunpcklpd\t{%2, %1, %0|%0, %1, %2} + vunpcklpd\t{%2, %1, %0|%0, %1, %2} %vmovddup\t{%1, %0|%0, %1} + vmovddup\t{%1, %0|%0, %1} movhpd\t{%2, %0|%0, %2} vmovhpd\t{%2, %1, %0|%0, %1, %2} %vmovsd\t{%1, %0|%0, %1} movlhps\t{%2, %0|%0, %2} movhps\t{%2, %0|%0, %2}" - [(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx") + [(set_attr "isa" "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx") (set (attr "type") (if_then_else (eq_attr "alternative" "0,1,2") (const_string "sselog") (const_string "ssemov"))) - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*") - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig") - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")]) + (set (attr "prefix_data16") + (if_then_else (eq_attr "alternative" "5") + (const_string "1") + (const_string "*"))) + (set_attr "prefix" "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig") + (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;