public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
From: Segher Boessenkool <segher@kernel.crashing.org>
To: Richard Henderson <rth@redhat.com>
Cc: gcc-patches@gcc.gnu.org, David Edelsohn <dje.gcc@gmail.com>
Subject: Re: [PATCH 01/15] rs6000: Split out rs6000_is_valid_and_mask_wide
Date: Wed, 12 Aug 2015 13:24:00 -0000	[thread overview]
Message-ID: <20150812132355.GF4711@gate.crashing.org> (raw)
In-Reply-To: <1439341904-9345-2-git-send-email-rth@redhat.com>

On Tue, Aug 11, 2015 at 06:11:30PM -0700, Richard Henderson wrote:
> This allows testing for a mask without having to call GEN_INT.
> 
> Cc: David Edelsohn <dje.gcc@gmail.com>
> ---
> 	* config/rs6000/rs6000.c (rs6000_is_valid_mask_wide): Split out from...
> 	(rs6000_is_valid_mask): ... here.
> 	(rs6000_is_valid_and_mask_wide): Split out from...
> 	(rs6000_is_valid_and_mask): ... here.

I don't like these "_wide" names much.  You could overload the shorter
name, if you really think creating some garbage const_int's is too much
overhead (it might well be if you use it a lot more in later patches).

The original functions really want rtx's since they are used like
predicates (so should look and behave like one); rs6000_is_valid_mask
itself is different (and a lousy name; suggestions welcome).

> -bool
> -rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
> +static bool
> +rs6000_is_valid_mask_wide (unsigned HOST_WIDE_INT val, int *b, int *e, int n)

But why change the mode parameter?  The code was clearer before.

>  {
> -  unsigned HOST_WIDE_INT val = INTVAL (mask);
>    unsigned HOST_WIDE_INT bit;
>    int nb, ne;
> -  int n = GET_MODE_PRECISION (mode);
>  
> -  if (mode != DImode && mode != SImode)
> -    return false;
> -
> -  if (INTVAL (mask) >= 0)
> +  if ((HOST_WIDE_INT)val >= 0)
                        ^ missing space

>      {
>        bit = val & -val;
>        ne = exact_log2 (bit);
> @@ -16430,27 +16427,54 @@ rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
>    return true;
>  }
>  
> +bool
> +rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
> +{
> +  int n;
> +
> +  if (mode == DImode)
> +    n = 64;
> +  else if (mode == SImode)
> +    n = 32;
> +  else
> +    return false;
> +
> +  unsigned HOST_WIDE_INT val = INTVAL (mask);
> +  return rs6000_is_valid_mask_wide (val, b, e, n);
> +}
> +
>  /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
>     or rldicr instruction, to implement an AND with it in mode MODE.  */
>  
> -bool
> -rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
> +static bool
> +rs6000_is_valid_and_mask_wide (unsigned HOST_WIDE_INT val, machine_mode mode)
>  {
>    int nb, ne;
>  
> -  if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
> -    return false;
> +  switch (mode)
> +    {
> +    case DImode:
> +      if (!rs6000_is_valid_mask_wide (val, &nb, &ne, 64))
> +	return false;
> +      /* For DImode, we need a rldicl, rldicr, or a rlwinm with
> +	 mask that does not wrap.  */
> +      return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
>  
> -  /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
> -     does not wrap.  */
> -  if (mode == DImode)
> -    return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
> +    case SImode:
> +      if (!rs6000_is_valid_mask_wide (val, &nb, &ne, 32))
> +	return false;
> +      /* For SImode, rlwinm can do everything.  */
> +      return (nb < 32 && ne < 32);
>  
> -  /* For SImode, rlwinm can do everything.  */
> -  if (mode == SImode)
> -    return (nb < 32 && ne < 32);
> +    default:
> +      return false;
> +    }
> +}
>  
> -  return false;

You don't need any of these changes then, either.

> +bool
> +rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
> +{
> +  return rs6000_is_valid_and_mask_wide (UINTVAL (mask), mode);
>  }
>  
>  /* Return the instruction template for an AND with mask in mode MODE, with
> @@ -16739,12 +16763,12 @@ rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
>  
>    /* Otherwise, fill in the lowest "hole"; if we can do the result with
>       one insn, we can do the whole thing with two.  */
> -  unsigned HOST_WIDE_INT val = INTVAL (c);
> +  unsigned HOST_WIDE_INT val = UINTVAL (c);

Does it matter?


Segher

  reply	other threads:[~2015-08-12 13:24 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-12  1:11 [PATCH ppc64,aarch64,alpha 00/15] Improve backend constant generation Richard Henderson
2015-08-12  1:11 ` [PATCH 01/15] rs6000: Split out rs6000_is_valid_and_mask_wide Richard Henderson
2015-08-12 13:24   ` Segher Boessenkool [this message]
2015-08-12 15:50     ` Richard Henderson
2015-08-13  2:29       ` Segher Boessenkool
2015-08-12  1:11 ` [PATCH 05/15] rs6000: Move constant via mask into build_set_const_data Richard Henderson
2015-08-12  1:12 ` [PATCH 13/15] alpha: Use hashing infrastructure for generating constants Richard Henderson
2015-08-12  1:12 ` [PATCH 15/15] alpha: Remove alpha_emit_set_long_const Richard Henderson
2015-08-12  1:12 ` [PATCH 12/15] aarch64: Test for duplicated 32-bit halves Richard Henderson
2015-08-12  1:12 ` [PATCH 09/15] rs6000: Use xoris in constant construction Richard Henderson
2015-08-12  1:12 ` [PATCH 04/15] rs6000: Implement set_const_data infrastructure Richard Henderson
2015-08-12 13:53   ` Segher Boessenkool
2015-08-12  1:12 ` [PATCH 02/15] rs6000: Make num_insns_constant_wide static Richard Henderson
2015-08-12  1:12 ` [PATCH 03/15] rs6000: Tidy num_insns_constant vs CONST_DOUBLE Richard Henderson
2015-08-12  1:12 ` [PATCH 08/15] rs6000: Generalize masking in constant generation Richard Henderson
2015-08-12  1:12 ` [PATCH 06/15] rs6000: Use rldiwi in constant construction Richard Henderson
2015-08-12 14:02   ` Segher Boessenkool
2015-08-12 15:55     ` Richard Henderson
2015-08-13  2:43       ` Segher Boessenkool
2015-08-13 19:01         ` Mike Stump
2015-08-13 20:30           ` Joseph Myers
2015-08-12  1:12 ` [PATCH 11/15] aarch64: Use hashing infrastructure for generating constants Richard Henderson
2015-08-12  1:12 ` [PATCH 10/15] rs6000: Use rotldi in constant generation Richard Henderson
2015-08-12  1:12 ` [PATCH 07/15] rs6000: Generalize left shift " Richard Henderson
2015-08-12  1:12 ` [PATCH 14/15] alpha: Split out alpha_cost_set_const Richard Henderson
2015-08-12  8:32 ` [PATCH ppc64,aarch64,alpha 00/15] Improve backend constant generation Segher Boessenkool
2015-08-12 15:32   ` Richard Henderson
2015-08-13  3:07     ` Segher Boessenkool
2015-08-13  5:36       ` Segher Boessenkool
2015-08-13  3:10   ` Segher Boessenkool
2015-08-13 11:32     ` David Edelsohn
2015-08-12  8:32 ` Richard Earnshaw
2015-08-12  8:43   ` Richard Earnshaw
2015-08-12  9:02     ` Richard Earnshaw
2015-08-12 15:45   ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20150812132355.GF4711@gate.crashing.org \
    --to=segher@kernel.crashing.org \
    --cc=dje.gcc@gmail.com \
    --cc=gcc-patches@gcc.gnu.org \
    --cc=rth@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).