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* [PATCH] Missing Skylake -march=/-mtune= option
@ 2015-08-13  9:36 Yuri Rumyantsev
  2015-08-13 20:05 ` Uros Bizjak
  2015-08-20 15:52 ` Markus Trippelsdorf
  0 siblings, 2 replies; 7+ messages in thread
From: Yuri Rumyantsev @ 2015-08-13  9:36 UTC (permalink / raw)
  To: gcc-patches, Uros Bizjak, Igor Zamyatin,
	Илья
	Энкович

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Hi All,

Here is patch for adding march/mtune options for Skylake.

Bootstrap and regression testing did not show any new failures.

Is it OK for trunk?

ChangeLog:
2015-08-13  Yuri Rumyantsev  <ysrumyan@gmail.com>

* config/i386/driver-i386.c (host_detect_local_cpu): Add support
for skylake.
* config/i386/i386.c (PTA_SKYLAKE): New macros.
(processor_alias_table): Add skylake description.
(enum processor_model): Add skylake processor.
(arch_names_table): Add skylake record.
* doc/invoke.texi: Add skylake item.

gcc/testsuite/ChangeLog:
* gcc.target/i386/builtin_target.c: Add skylake check.

libgcc/ChangeLog:
* config/i386/cpuinfo.c (enum processor_subtypes): Add skylake.
(get_intel_cpu): Likewise.

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diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index bc5239e..ec4cbec 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -755,6 +755,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 	  /* Broadwell.  */
 	  cpu = "broadwell";
 	  break;
+	case 0x4e:
+	case 0x5e:
+	  /* Skylake.  */
+	  cpu = "skylake";
+	  break;
 	case 0x57:
 	  /* Knights Landing.  */
 	  cpu = "knl";
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
old mode 100644
new mode 100755
index 57d874b..3680a55
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -3285,6 +3285,8 @@ ix86_option_override_internal (bool main_args_p,
    | PTA_FMA | PTA_MOVBE | PTA_HLE)
 #define PTA_BROADWELL \
   (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
+#define PTA_SKYLAKE \
+  (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
 #define PTA_KNL \
   (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
 #define PTA_BONNELL \
@@ -3347,6 +3349,7 @@ ix86_option_override_internal (bool main_args_p,
       {"haswell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
       {"core-avx2", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_HASWELL},
       {"broadwell", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_BROADWELL},
+      {"skylake", PROCESSOR_HASWELL, CPU_NEHALEM, PTA_SKYLAKE},
       {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
       {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
       {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
@@ -35633,7 +35636,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
     M_AMDFAM15H_BDVER4,
     M_INTEL_COREI7_IVYBRIDGE,
     M_INTEL_COREI7_HASWELL,
-    M_INTEL_COREI7_BROADWELL
+    M_INTEL_COREI7_BROADWELL,
+    M_INTEL_COREI7_SKYLAKE
   };
 
   static struct _arch_names_table
@@ -35655,6 +35659,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
       {"ivybridge", M_INTEL_COREI7_IVYBRIDGE},
       {"haswell", M_INTEL_COREI7_HASWELL},
       {"broadwell", M_INTEL_COREI7_BROADWELL},
+      {"skylake", M_INTEL_COREI7_SKYLAKE},
       {"bonnell", M_INTEL_BONNELL},
       {"silvermont", M_INTEL_SILVERMONT},
       {"knl", M_INTEL_KNL},
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c26cd87..316ecce 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22403,6 +22403,12 @@ Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
 BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
 
+@item skylake
+Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
+XSAVES instruction set support.
+
 @item bonnell
 Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c
index 4adea27..2284f52 100644
--- a/gcc/testsuite/gcc.target/i386/builtin_target.c
+++ b/gcc/testsuite/gcc.target/i386/builtin_target.c
@@ -81,6 +81,12 @@ check_intel_cpu_model (unsigned int family, unsigned int model,
 	      assert (__builtin_cpu_is ("corei7"));
 	      assert (__builtin_cpu_is ("broadwell"));
 	      break;
+	    case 0x4e:
+	    case 0x5e:
+	      /* Skylake.  */
+	      assert (__builtin_cpu_is ("corei7"));
+	      assert (__builtin_cpu_is ("skylake"));
+	      break;
 	    case 0x17:
 	    case 0x1d:
 	      /* Penryn.  */
diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c
index 57711d0..0f8df3a 100644
--- a/libgcc/config/i386/cpuinfo.c
+++ b/libgcc/config/i386/cpuinfo.c
@@ -76,6 +76,7 @@ enum processor_subtypes
   INTEL_COREI7_IVYBRIDGE,
   INTEL_COREI7_HASWELL,
   INTEL_COREI7_BROADWELL,
+  INTEL_COREI7_SKYLAKE,
   CPU_SUBTYPE_MAX
 };
 
@@ -239,6 +240,12 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
 	      __cpu_model.__cpu_type = INTEL_COREI7;
 	      __cpu_model.__cpu_subtype = INTEL_COREI7_BROADWELL;
 	      break;
+	    case 0x4e:
+	    case 0x5e:
+	      /* Skylake.  */
+	      __cpu_model.__cpu_type = INTEL_COREI7;
+	      __cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE;
+	      break;
 	    case 0x17:
 	    case 0x1d:
 	      /* Penryn.  */

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2015-08-23 10:54 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-13  9:36 [PATCH] Missing Skylake -march=/-mtune= option Yuri Rumyantsev
2015-08-13 20:05 ` Uros Bizjak
2015-08-19 10:47   ` Richard Biener
2015-08-19 11:11     ` Uros Bizjak
2015-08-19 11:39       ` Richard Biener
2015-08-20 15:52 ` Markus Trippelsdorf
2015-08-23 14:46   ` Markus Trippelsdorf

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