From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22803 invoked by alias); 31 Aug 2015 17:49:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 22792 invoked by uid 89); 31 Aug 2015 17:49:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.3 required=5.0 tests=AWL,BAYES_50,KAM_LAZY_DOMAIN_SECURITY,RDNS_DYNAMIC,TVD_RCVD_IP autolearn=no version=3.3.2 X-HELO: brightrain.aerifal.cx Received: from 216-12-86-13.cv.mvl.ntelos.net (HELO brightrain.aerifal.cx) (216.12.86.13) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 31 Aug 2015 17:49:12 +0000 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1ZWTCf-00027l-00 for gcc-patches@gcc.gnu.org; Mon, 31 Aug 2015 17:49:09 +0000 Date: Mon, 31 Aug 2015 17:52:00 -0000 From: Rich Felker To: gcc-patches@gcc.gnu.org Subject: [PATCH] add initial support for J2 core to sh target Message-ID: <20150831174909.GA6317@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="SUOF0GtieIMvvwua" Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2015-08/txt/msg01897.txt.bz2 --SUOF0GtieIMvvwua Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-length: 1563 The J2 Core is an open hardware cpu implementing the SH-2 instruction set, with the addition of barrel shift instructions and an atomic compare-and-swap instruction. This patch adds a cpu model option -mj2 to the sh target. Presently all it does is enable use of the barrel shift instructions (and turns off assembler checking of the ISA via --isa=any) but I will eventually add support for the new CAS instruction as a new -matomic-model for use by the __sync and __atomic builtins. I've used the the name "J2" and "-mj2" rather than treating it as a submodel variant of "sh2" ("SH2J" and "-m2j") because the official name of this cpu model is "J2", with the intent of not misrepresenting it as a Renesas product. However I'd like feedback from GCC's side on how GCC wants to identify J2 in cpu model options, tuples, and internally; that part is not set in stone. The --isa=any passed to the assembler probably needs to be fixed before this patch is ready for upstream (although I'd really just prefer _always_ passing --isa=any to the assembler, since the current behavior breaks runtime-switching implementations, which I need). One complication is that passing --isa=j2 will fail with old binutils; I'm not sure if this should be detected and handled or if we should just require up-to-date binutils to use -mj2. In any case, I don't yet have an assembler-side patch to add the --isa level. I know this isn't ready for upstream yet but I'd appreciate feedback on the patch so far and anything that I need to change in order for it to be acceptable. Rich --SUOF0GtieIMvvwua Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="0004-j2.diff" Content-length: 3642 --- gcc-5.2.0.orig/gcc/config.gcc +++ gcc-5.2.0/gcc/config.gcc @@ -2668,7 +2671,7 @@ sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ - sh3e | sh3 | sh2e | sh2 | sh1) ;; + sh3e | sh3 | sh2e | sh2 | sh1 | shj2 ) ;; "") sh_cpu_default=${sh_cpu_target} ;; *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; esac @@ -2687,9 +2690,9 @@ sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" fi fi - target_cpu_default=SELECT_`echo ${sh_cpu_default}|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_` + target_cpu_default=SELECT_`echo ${sh_cpu_default}|sed 's/^shj/j/'|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_` tm_defines=${tm_defines}' SH_MULTILIB_CPU_DEFAULT=\"'`echo $sh_cpu_default|sed s/sh/m/`'\"' - tm_defines="$tm_defines SUPPORT_`echo $sh_cpu_default | sed 's/^m/sh/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1" + tm_defines="$tm_defines SUPPORT_`echo $sh_cpu_default | sed -e 's/^m/sh/' -e 's/^shj/j/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1" sh_multilibs=`echo $sh_multilibs | sed -e 's/,/ /g' -e 's/^[Ss][Hh]/m/' -e 's/ [Ss][Hh]/ m/g' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz-` for sh_multilib in ${sh_multilibs}; do case ${sh_multilib} in @@ -4106,6 +4109,8 @@ ;; m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) ;; + mj2) + ;; *) echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 --- gcc-5.2.0.orig/gcc/config/sh/sh.h +++ gcc-5.2.0/gcc/config/sh/sh.h @@ -139,6 +139,7 @@ #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ | MASK_SH2 | MASK_SH1) +#define SELECT_J2 (MASK_SH2 | MASK_J2 | SELECT_SH1) #define SELECT_SH3 (MASK_SH3 | SELECT_SH2) #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) @@ -162,6 +163,9 @@ #define SUPPORT_SH2 1 #endif #if SUPPORT_SH2 +#define SUPPORT_J2 1 +#endif +#ifdef SUPPORT_J2 #define SUPPORT_SH3 1 #define SUPPORT_SH2A_NOFPU 1 #endif @@ -211,7 +215,7 @@ #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \ - | MASK_FPU_SINGLE_ONLY) + | MASK_FPU_SINGLE_ONLY | MASK_J2) /* This defaults us to big-endian. */ #ifndef TARGET_ENDIAN_DEFAULT @@ -271,6 +275,7 @@ %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ %{m1:--isa=sh} \ %{m2:--isa=sh2} \ +%{mj2:--isa=any} \ %{m2e:--isa=sh2e} \ %{m3:--isa=sh3} \ %{m3e:--isa=sh3e} \ @@ -1834,7 +1839,7 @@ /* Nonzero if the target supports dynamic shift instructions like shad and shld. */ -#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) +#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_J2) /* The cost of using the dynamic shift insns (shad, shld) are the same if they are available. If they are not available a library function will --- gcc-5.2.0.orig/gcc/config/sh/sh.opt +++ gcc-5.2.0/gcc/config/sh/sh.opt @@ -71,6 +71,10 @@ Target RejectNegative Condition(SUPPORT_SH2E) Generate SH2e code +mj2 +Target RejectNegative Mask(J2) Condition(SUPPORT_J2) +Generate J2 code + m3 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) Generate SH3 code --SUOF0GtieIMvvwua--