From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6397 invoked by alias); 11 Sep 2015 15:31:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 6365 invoked by uid 89); 11 Sep 2015 15:31:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 11 Sep 2015 15:31:50 +0000 Received: from arm.com (e107456-lin.cambridge.arm.com [10.2.207.14]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id t8BFVk1n020006; Fri, 11 Sep 2015 16:31:46 +0100 Date: Fri, 11 Sep 2015 15:38:00 -0000 From: James Greenhalgh To: Kyrill Tkachov Cc: GCC Patches , Marcus Shawcroft , Richard Earnshaw Subject: Re: [PATCH][AArch64] Use preferred aliases for CSNEG, CSINC, CSINV Message-ID: <20150911153146.GA5206@arm.com> References: <55E5790A.2090205@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <55E5790A.2090205@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2015-09/txt/msg00815.txt.bz2 On Tue, Sep 01, 2015 at 11:08:10AM +0100, Kyrill Tkachov wrote: > Hi all, > > The ARMv8-A reference manual says: > "CNEG , , > is equivalent to > CSNEG , , , invert() > and is the preferred disassembly when Rn == Rm && cond != '111x'." > > That is, when the two input registers are the same we can use the shorter CNEG mnemonic > with the inverse condition instead of the longer CSNEG instruction. Similarly for the > CSINV and CSINC instructions, they have shorter CINV and CINC forms. > This patch adjusts the output templates to emit the preferred shorter sequences when possible. > > The new mnemonics are just aliases, they map down to the same instruction in the end, so there > are no performance or behaviour implications. But it does make the assembly a bit more readable > IMO, since: > "cneg w27, w9, le" > can be simply read as "if the condition is less or equal negate w9" instead of the previous: > "csneg w27, w9, w9, gt" where you have to remember which of the input registers is negated. > > > Bootstrapped and tested on aarch64-linux-gnu. > Ok for trunk? > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 77bc7cd..2e4b26c 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -3090,7 +3090,12 @@ (define_insn "csinc3_insn" > (const_int 1)) > (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")))] > "" > - "csinc\\t%0, %3, %2, %M1" > + { > + if (rtx_equal_p (operands[2], operands[3])) > + return "cinc\\t%0, %2, %m1"; > + else > + return "csinc\\t%0, %3, %2, %M1"; > + } > [(set_attr "type" "csel")] > ) I guess you do it this way rather than just adding a new alternative in the pattern to avoid any chance of constraining the register allocator, but would this not be more natural to read as an {r, r, r, 2} alternative, or similar? If you've given that some thought and decided it doesn't work for you, then this is OK for trunk. Thanks, James