* [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
@ 2015-10-01 11:12 Kirill Yukhin
2015-10-02 14:38 ` Kirill Yukhin
0 siblings, 1 reply; 9+ messages in thread
From: Kirill Yukhin @ 2015-10-01 11:12 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
Hello,
Patch in the bottom improves insns sequences for
strided loads.
E.g. on `-march=skylake-avx512' for this test:
unsigned char yy[10000];
unsigned char xx[10000];
void
__attribute__ ((noinline)) generateMTFValues (unsigned char s)
{
unsigned char i;
for (i = 0; i < s; i++)
yy[i] = xx [i*2 + 1];
}
We have:
vmovdqa64 .LC0(%rip), %zmm0 # 34 *movv32hi_internal/2 [length = 11]
vmovdqa64 .LC1(%rip), %zmm1 # 36 *movv32hi_internal/2 [length = 11]
vmovdqu64 xx+1(%rip), %zmm3 # 29 *movv64qi_internal/2 [length = 11]
vmovdqu64 xx+65(%rip), %zmm4 # 32 *movv64qi_internal/2 [length = 11]
vmovdqa64 %zmm0, %zmm2 # 153 *movv32hi_internal/2 [length = 6]
vmovdqa64 %zmm1, %zmm5 # 155 *movv32hi_internal/2 [length = 6]
vpermi2w %zmm4, %zmm3, %zmm2 # 35 avx512bw_vpermi2varv32hi3 [length = 6]
vpermi2w %zmm4, %zmm3, %zmm5 # 37 avx512bw_vpermi2varv32hi3 [length = 6]
vmovdqa64 .LC2(%rip), %zmm4 # 38 *movv64qi_internal/2 [length = 11]
vmovdqa64 .LC3(%rip), %zmm3 # 40 *movv64qi_internal/2 [length = 11]
vpshufb %zmm4, %zmm2, %zmm2 # 39 avx512bw_pshufbv64qi3/2 [length = 6]
vpshufb %zmm3, %zmm5, %zmm5 # 41 avx512bw_pshufbv64qi3/2 [length = 6]
vporq %zmm5, %zmm2, %zmm2 # 42 *iorv64qi3/2 [length = 4]
vmovdqu32 %zmm2, yy(%rip) # 44 avx512f_storedquv16si [length = 11]
Due to most common permute expander got in charge.
Patch reduces the code to:
vmovdqu64 xx+1(%rip), %zmm0 # 28 *movv16si_internal/2 [length = 11]
vmovdqu64 xx+65(%rip), %zmm1 # 134 *movv16si_internal/2 [length = 11]
vpmovwb %zmm0, %ymm0 # 34 avx512bw_truncatev32hiv32qi2/1 [length = 6]
vpmovwb %zmm1, %ymm1 # 35 avx512bw_truncatev32hiv32qi2/1 [length = 6]
vinserti64x4 $0x1, %ymm1, %zmm0, %zmm0 # 36 avx_vec_concatv64qi/1 [length = 7]
vmovdqu32 %zmm0, yy(%rip) # 38 avx512f_storedquv16si [length = 11]
Also it allows to do extract_even_odd for V64QI.
Bootstrapped. New tests pass (fail w/o the change). Regtesting is in progress.
Is it ok for trunk?
gcc/
* config/i386/i386.c (expand_vec_perm_even_odd_trunc): New.
(expand_vec_perm_even_odd_1): Handle V64QImode.
(ix86_expand_vec_perm_const_1): Try expansion with
expand_vec_perm_even_odd_trunc as well.
* config/i386/sse.md (VI124_AVX512F): Rename to ...
(define_mode_iterator VI124_AVX2_24_AVX512F_1_AVX512BW): This. Extend
to V54QI.
(define_mode_iterator VI248_AVX2_8_AVX512F): Rename to ...
(define_mode_iterator VI248_AVX2_8_AVX512F_24_AVX512BW): This. Extend
to V32HI and V16SI.
(define_insn "avx512bw_<code>v32hiv32qi2"): Unhide pattern name.
(define_expand "vec_pack_trunc_<mode>"): Update iterator name.
(define_expand "vec_unpacks_lo_<mode>"): Ditto.
(define_expand "vec_unpacks_hi_<mode>"): Ditto.
(define_expand "vec_unpacku_lo_<mode>"): Ditto.
(define_expand "vec_unpacku_hi_<mode>"): Ditto.
gcc/testsuite/
* gcc.target/i386/vect-pack-trunc-1.c: New test.
* gcc.target/i386/vect-pack-trunc-2.c: Ditto.
* gcc.target/i386/vect-perm-even-1.c: Ditto.
* gcc.target/i386/vect-perm-odd-1.c: Ditto.
* gcc.target/i386/vect-unpack-1.c: Ditto.
* gcc.target/i386/vect-unpack-2.c: Ditto.
--
Thanks, K
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d370521..24202b3 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -49216,6 +49216,62 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d *d)
return true;
}
+/* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
+ and extract-odd permutations of two V64QI operands
+ with two "shifts", two "truncs" and one "concat" insns for "odd"
+ and two "truncs" and one concat insn for "even."
+ Have already failed all two instruction sequences. */
+
+static bool
+expand_vec_perm_even_odd_trunc (struct expand_vec_perm_d *d)
+{
+ rtx t1, t2, t3, t4;
+ unsigned i, odd, nelt = d->nelt;
+
+ if (!TARGET_AVX512BW
+ || d->one_operand_p
+ || d->vmode != V64QImode)
+ return false;
+
+ /* Check that permutation is even or odd. */
+ odd = d->perm[0];
+ if (odd > 1)
+ return false;
+
+ for (i = 1; i < nelt; ++i)
+ if (d->perm[i] != 2 * i + odd)
+ return false;
+
+ if (d->testing_p)
+ return true;
+
+
+ if (odd)
+ {
+ t1 = gen_reg_rtx (V32HImode);
+ t2 = gen_reg_rtx (V32HImode);
+ emit_insn (gen_lshrv32hi3 (t1,
+ gen_lowpart (V32HImode, d->op0),
+ GEN_INT (8)));
+ emit_insn (gen_lshrv32hi3 (t2,
+ gen_lowpart (V32HImode, d->op1),
+ GEN_INT (8)));
+ }
+ else
+ {
+ t1 = gen_lowpart (V32HImode, d->op0);
+ t2 = gen_lowpart (V32HImode, d->op1);
+ }
+
+ t3 = gen_reg_rtx (V32QImode);
+ t4 = gen_reg_rtx (V32QImode);
+ emit_insn (gen_avx512bw_truncatev32hiv32qi2 (t3, t1));
+ emit_insn (gen_avx512bw_truncatev32hiv32qi2 (t4, t2));
+ emit_insn (gen_avx_vec_concatv64qi (d->target, t3, t4));
+
+ return true;
+}
+
/* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
and extract-odd permutations. */
@@ -49318,6 +49374,9 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd)
case V32QImode:
return expand_vec_perm_even_odd_pack (d);
+ case V64QImode:
+ return expand_vec_perm_even_odd_trunc (d);
+
case V4DImode:
if (!TARGET_AVX2)
{
@@ -49779,6 +49838,8 @@ ix86_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
/* Try sequences of four instructions. */
+ if (expand_vec_perm_even_odd_trunc (d))
+ return true;
if (expand_vec_perm_vpshufb2_vpermq (d))
return true;
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 4eefb45..013681c 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -381,8 +381,8 @@
[(V16HI "TARGET_AVX2") V8HI
(V8SI "TARGET_AVX2") V4SI])
-(define_mode_iterator VI124_AVX512F
- [(V32QI "TARGET_AVX2") V16QI
+(define_mode_iterator VI124_AVX2_24_AVX512F_1_AVX512BW
+ [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI
(V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI
(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI])
@@ -398,9 +398,9 @@
[(V8SI "TARGET_AVX2") V4SI
(V4DI "TARGET_AVX2") V2DI])
-(define_mode_iterator VI248_AVX2_8_AVX512F
- [(V16HI "TARGET_AVX2") V8HI
- (V8SI "TARGET_AVX2") V4SI
+(define_mode_iterator VI248_AVX2_8_AVX512F_24_AVX512BW
+ [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI
+ (V16SI "TARGET_AVX512BW") (V8SI "TARGET_AVX2") V4SI
(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI])
(define_mode_iterator VI248_AVX512BW_AVX512VL
@@ -8749,7 +8749,7 @@
(match_operand:<avx512fmaskmode> 2 "register_operand")))]
"TARGET_AVX512F")
-(define_insn "*avx512bw_<code>v32hiv32qi2"
+(define_insn "avx512bw_<code>v32hiv32qi2"
[(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m")
(any_truncate:V32QI
(match_operand:V32HI 1 "register_operand" "v,v")))]
@@ -11331,8 +11331,8 @@
(define_expand "vec_pack_trunc_<mode>"
[(match_operand:<ssepackmode> 0 "register_operand")
- (match_operand:VI248_AVX2_8_AVX512F 1 "register_operand")
- (match_operand:VI248_AVX2_8_AVX512F 2 "register_operand")]
+ (match_operand:VI248_AVX2_8_AVX512F_24_AVX512BW 1 "register_operand")
+ (match_operand:VI248_AVX2_8_AVX512F_24_AVX512BW 2 "register_operand")]
"TARGET_SSE2"
{
rtx op1 = gen_lowpart (<ssepackmode>mode, operands[1]);
@@ -13221,25 +13221,25 @@
(define_expand "vec_unpacks_lo_<mode>"
[(match_operand:<sseunpackmode> 0 "register_operand")
- (match_operand:VI124_AVX512F 1 "register_operand")]
+ (match_operand:VI124_AVX2_24_AVX512F_1_AVX512BW 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
(define_expand "vec_unpacks_hi_<mode>"
[(match_operand:<sseunpackmode> 0 "register_operand")
- (match_operand:VI124_AVX512F 1 "register_operand")]
+ (match_operand:VI124_AVX2_24_AVX512F_1_AVX512BW 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
(define_expand "vec_unpacku_lo_<mode>"
[(match_operand:<sseunpackmode> 0 "register_operand")
- (match_operand:VI124_AVX512F 1 "register_operand")]
+ (match_operand:VI124_AVX2_24_AVX512F_1_AVX512BW 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
(define_expand "vec_unpacku_hi_<mode>"
[(match_operand:<sseunpackmode> 0 "register_operand")
- (match_operand:VI124_AVX512F 1 "register_operand")]
+ (match_operand:VI124_AVX2_24_AVX512F_1_AVX512BW 1 "register_operand")]
"TARGET_SSE2"
"ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
diff --git a/gcc/testsuite/gcc.target/i386/vect-pack-trunc-1.c b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-1.c
new file mode 100644
index 0000000..774d4bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+
+#include "avx512bw-check.h"
+
+#define N 400
+unsigned char yy[10000];
+
+void
+__attribute__ ((noinline)) foo (unsigned short s)
+{
+ unsigned short i;
+ for (i = 0; i < s; i++)
+ yy[i] = (unsigned char) i;
+}
+
+void
+avx512bw_test ()
+{
+ unsigned short i;
+ foo (N);
+
+ for (i = 0; i < N; i++)
+ if ( (unsigned char)i != yy [i] )
+ abort ();
+}
+
+/* { dg-final { scan-assembler-times "vpmovwb\[ \\t\]+\[^\n\]*%zmm" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-pack-trunc-2.c b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-2.c
new file mode 100644
index 0000000..a1a075f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-pack-trunc-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+
+#include "avx512bw-check.h"
+
+#define N 400
+unsigned short yy[10000];
+
+void
+__attribute__ ((noinline)) foo (unsigned int s)
+{
+ unsigned int i;
+ for (i = 0; i < s; i++)
+ yy[i] = (unsigned short) i;
+}
+
+void
+avx512bw_test ()
+{
+ unsigned int i;
+ foo (N);
+ for (i = 0; i < N; i++)
+ if ( (unsigned short)i != yy [i] )
+ abort ();
+}
+
+/* { dg-final { scan-assembler-times "vpermi2w\[ \\t\]+\[^\n\]*%zmm" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-perm-even-1.c b/gcc/testsuite/gcc.target/i386/vect-perm-even-1.c
new file mode 100644
index 0000000..a2ff73d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-perm-even-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+
+#include "avx512bw-check.h"
+
+#define N 400
+unsigned char yy[10000];
+unsigned char xx[10000];
+
+void
+__attribute__ ((noinline)) foo (unsigned short s)
+{
+ unsigned short i;
+ for (i = 0; i < s; i++)
+ yy[i] = xx [i*2 + 1];
+}
+
+void
+avx512bw_test ()
+{
+ unsigned short i;
+ unsigned char j = 0;
+ for (i = 0; i < 2 * N + 1; i++, j++)
+ xx [i] = j;
+
+ foo (N);
+
+ for (i = 0; i < N; i++)
+ if ( (unsigned char)(2*i+1) != yy [i] )
+ abort ();
+}
+
+/* { dg-final { scan-assembler-times "vpmovwb\[ \\t\]+\[^\n\]*%zmm" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-perm-odd-1.c b/gcc/testsuite/gcc.target/i386/vect-perm-odd-1.c
new file mode 100644
index 0000000..65f1a80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-perm-odd-1.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+
+#include "avx512bw-check.h"
+
+#define N 400
+
+typedef struct
+{
+ unsigned char real;
+ unsigned char imag;
+} complex8_t;
+
+void
+__attribute__ ((noinline)) foo (unsigned char *a,
+ complex8_t *x, unsigned len)
+{
+ unsigned i;
+ for (i = 0; i < len; i++)
+ a[i] = x[i].imag + x[i].real;
+}
+
+void
+avx512bw_test ()
+{
+ unsigned short i;
+ unsigned char j = 0;
+ complex8_t x [N];
+ unsigned char a [N];
+
+ for (i = 0; i < N; i++, j++)
+ {
+ x [i].real = j;
+ x [i].imag = j;
+ }
+
+ foo (a, x, N);
+
+ j = 0;
+ for (i = 0; i < N; i++, j++)
+ if ( a[i] != (unsigned char)(j+j) )
+ abort ();
+}
+
+/* { dg-final { scan-assembler-times "vpmovwb\[ \\t\]+\[^\n\]*%zmm" 4 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-unpack-1.c b/gcc/testsuite/gcc.target/i386/vect-unpack-1.c
new file mode 100644
index 0000000..eedca47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-unpack-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+
+#include "avx512bw-check.h"
+
+#define N 255
+unsigned int yy[10000];
+
+void
+__attribute__ ((noinline)) foo (unsigned char s)
+{
+ unsigned char i;
+ for (i = 0; i < s; i++)
+ yy[i] = (unsigned int) i;
+}
+
+void
+avx512bw_test ()
+{
+ unsigned char i;
+ foo (N);
+ for (i = 0; i < N; i++)
+ if ( (unsigned int)i != yy [i] )
+ abort ();
+}
+
+/* { dg-final { scan-assembler-times "vpmovzxbw\[ \\t\]+\[^\n\]*%zmm" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-unpack-2.c b/gcc/testsuite/gcc.target/i386/vect-unpack-2.c
new file mode 100644
index 0000000..b825f0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-unpack-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+
+#include "avx512bw-check.h"
+
+#define N 120
+signed int yy[10000];
+
+void
+__attribute__ ((noinline)) foo (signed char s)
+{
+ signed char i;
+ for (i = 0; i < s; i++)
+ yy[i] = (signed int) i;
+}
+
+void
+avx512bw_test ()
+{
+ signed char i;
+ foo (N);
+ for (i = 0; i < N; i++)
+ if ( (signed int)i != yy [i] )
+ abort ();
+}
+
+/* { dg-final { scan-assembler-times "vpmovsxbw\[ \\t\]+\[^\n\]*%zmm" 2 } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
2015-10-01 11:12 [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns Kirill Yukhin
@ 2015-10-02 14:38 ` Kirill Yukhin
2015-10-06 11:05 ` H.J. Lu
0 siblings, 1 reply; 9+ messages in thread
From: Kirill Yukhin @ 2015-10-02 14:38 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On 01 Oct 14:11, Kirill Yukhin wrote:
> Bootstrapped. New tests pass (fail w/o the change). Regtesting is in progress.
>
> Is it ok for trunk?
>
> gcc/
> * config/i386/i386.c (expand_vec_perm_even_odd_trunc): New.
> (expand_vec_perm_even_odd_1): Handle V64QImode.
> (ix86_expand_vec_perm_const_1): Try expansion with
> expand_vec_perm_even_odd_trunc as well.
> * config/i386/sse.md (VI124_AVX512F): Rename to ...
> (define_mode_iterator VI124_AVX2_24_AVX512F_1_AVX512BW): This. Extend
> to V54QI.
> (define_mode_iterator VI248_AVX2_8_AVX512F): Rename to ...
> (define_mode_iterator VI248_AVX2_8_AVX512F_24_AVX512BW): This. Extend
> to V32HI and V16SI.
> (define_insn "avx512bw_<code>v32hiv32qi2"): Unhide pattern name.
> (define_expand "vec_pack_trunc_<mode>"): Update iterator name.
> (define_expand "vec_unpacks_lo_<mode>"): Ditto.
> (define_expand "vec_unpacks_hi_<mode>"): Ditto.
> (define_expand "vec_unpacku_lo_<mode>"): Ditto.
> (define_expand "vec_unpacku_hi_<mode>"): Ditto.
>
> gcc/testsuite/
> * gcc.target/i386/vect-pack-trunc-1.c: New test.
> * gcc.target/i386/vect-pack-trunc-2.c: Ditto.
> * gcc.target/i386/vect-perm-even-1.c: Ditto.
> * gcc.target/i386/vect-perm-odd-1.c: Ditto.
> * gcc.target/i386/vect-unpack-1.c: Ditto.
> * gcc.target/i386/vect-unpack-2.c: Ditto.
Checked into main trunk. I'll also check it into gcc-5-branch
if no objections from RMs next ww.
--
Thanks, K
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
2015-10-02 14:38 ` Kirill Yukhin
@ 2015-10-06 11:05 ` H.J. Lu
2015-10-06 11:18 ` H.J. Lu
0 siblings, 1 reply; 9+ messages in thread
From: H.J. Lu @ 2015-10-06 11:05 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, GCC Patches
On Fri, Oct 2, 2015 at 7:37 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> On 01 Oct 14:11, Kirill Yukhin wrote:
>> Bootstrapped. New tests pass (fail w/o the change). Regtesting is in progress.
>>
>> Is it ok for trunk?
>>
>> gcc/
>> * config/i386/i386.c (expand_vec_perm_even_odd_trunc): New.
>> (expand_vec_perm_even_odd_1): Handle V64QImode.
>> (ix86_expand_vec_perm_const_1): Try expansion with
>> expand_vec_perm_even_odd_trunc as well.
>> * config/i386/sse.md (VI124_AVX512F): Rename to ...
>> (define_mode_iterator VI124_AVX2_24_AVX512F_1_AVX512BW): This. Extend
>> to V54QI.
>> (define_mode_iterator VI248_AVX2_8_AVX512F): Rename to ...
>> (define_mode_iterator VI248_AVX2_8_AVX512F_24_AVX512BW): This. Extend
>> to V32HI and V16SI.
>> (define_insn "avx512bw_<code>v32hiv32qi2"): Unhide pattern name.
>> (define_expand "vec_pack_trunc_<mode>"): Update iterator name.
>> (define_expand "vec_unpacks_lo_<mode>"): Ditto.
>> (define_expand "vec_unpacks_hi_<mode>"): Ditto.
>> (define_expand "vec_unpacku_lo_<mode>"): Ditto.
>> (define_expand "vec_unpacku_hi_<mode>"): Ditto.
>>
>> gcc/testsuite/
>> * gcc.target/i386/vect-pack-trunc-1.c: New test.
>> * gcc.target/i386/vect-pack-trunc-2.c: Ditto.
>> * gcc.target/i386/vect-perm-even-1.c: Ditto.
>> * gcc.target/i386/vect-perm-odd-1.c: Ditto.
>> * gcc.target/i386/vect-unpack-1.c: Ditto.
>> * gcc.target/i386/vect-unpack-2.c: Ditto.
> Checked into main trunk. I'll also check it into gcc-5-branch
> if no objections from RMs next ww.
>
This caused:
FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
on gcc-5-branch.
--
H.J.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
2015-10-06 11:05 ` H.J. Lu
@ 2015-10-06 11:18 ` H.J. Lu
2015-10-06 12:10 ` Kirill Yukhin
0 siblings, 1 reply; 9+ messages in thread
From: H.J. Lu @ 2015-10-06 11:18 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, GCC Patches
On Tue, Oct 6, 2015 at 4:05 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Fri, Oct 2, 2015 at 7:37 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
>> On 01 Oct 14:11, Kirill Yukhin wrote:
>>> Bootstrapped. New tests pass (fail w/o the change). Regtesting is in progress.
>>>
>>> Is it ok for trunk?
>>>
>>> gcc/
>>> * config/i386/i386.c (expand_vec_perm_even_odd_trunc): New.
>>> (expand_vec_perm_even_odd_1): Handle V64QImode.
>>> (ix86_expand_vec_perm_const_1): Try expansion with
>>> expand_vec_perm_even_odd_trunc as well.
>>> * config/i386/sse.md (VI124_AVX512F): Rename to ...
>>> (define_mode_iterator VI124_AVX2_24_AVX512F_1_AVX512BW): This. Extend
>>> to V54QI.
>>> (define_mode_iterator VI248_AVX2_8_AVX512F): Rename to ...
>>> (define_mode_iterator VI248_AVX2_8_AVX512F_24_AVX512BW): This. Extend
>>> to V32HI and V16SI.
>>> (define_insn "avx512bw_<code>v32hiv32qi2"): Unhide pattern name.
>>> (define_expand "vec_pack_trunc_<mode>"): Update iterator name.
>>> (define_expand "vec_unpacks_lo_<mode>"): Ditto.
>>> (define_expand "vec_unpacks_hi_<mode>"): Ditto.
>>> (define_expand "vec_unpacku_lo_<mode>"): Ditto.
>>> (define_expand "vec_unpacku_hi_<mode>"): Ditto.
>>>
>>> gcc/testsuite/
>>> * gcc.target/i386/vect-pack-trunc-1.c: New test.
>>> * gcc.target/i386/vect-pack-trunc-2.c: Ditto.
>>> * gcc.target/i386/vect-perm-even-1.c: Ditto.
>>> * gcc.target/i386/vect-perm-odd-1.c: Ditto.
>>> * gcc.target/i386/vect-unpack-1.c: Ditto.
>>> * gcc.target/i386/vect-unpack-2.c: Ditto.
>> Checked into main trunk. I'll also check it into gcc-5-branch
>> if no objections from RMs next ww.
>>
>
> This caused:
>
> FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
>
> on gcc-5-branch.
>
vect-perm-odd-1.s: Assembler messages:
vect-perm-odd-1.s:233: Error: operand type mismatch for `vpor'
vect-perm-odd-1.s:240: Error: operand type mismatch for `vpor'
vpor %zmm1, %zmm2, %zmm1
It should be
vporq %zmm1, %zmm2, %zmm1
--
H.J.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
2015-10-06 11:18 ` H.J. Lu
@ 2015-10-06 12:10 ` Kirill Yukhin
2015-10-08 5:14 ` Kirill Yukhin
0 siblings, 1 reply; 9+ messages in thread
From: Kirill Yukhin @ 2015-10-06 12:10 UTC (permalink / raw)
To: H.J. Lu; +Cc: Uros Bizjak, GCC Patches
> > This caused:
> >
> > FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
> >
> > on gcc-5-branch.
> >
>
> vect-perm-odd-1.s: Assembler messages:
> vect-perm-odd-1.s:233: Error: operand type mismatch for `vpor'
> vect-perm-odd-1.s:240: Error: operand type mismatch for `vpor'
>
> vpor %zmm1, %zmm2, %zmm1
>
> It should be
>
> vporq %zmm1, %zmm2, %zmm1
It looks like patch revealed issue w/ wrong `or' emit.
Patch of Alexander Fomin fixes it.
I've backported it for gcc-5.
Bootstrapped. Regtest in progress.
Is it ok for gcc-5 if regtesting pass?
(plan B is to revert causing commit from gcc-5)
--
Thanks, K
commit 6fb351df5ddc144a9a487b70bd9945d1e21a0033
Author: kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue Sep 22 11:14:25 2015 +0000
PR target/67480
gcc/
* config/i386/sse.md (define_mode_iterator VI48_AVX_AVX512F): New.
(define_mode_iterator VI12_AVX_AVX512F): New.
(define_insn "<mask_codefor><code><mode>3<mask_name>"): Change
all iterators to VI48_AVX_AVX512F. Extract remaining modes ...
(define_insn "*<code><mode>3"): ... Into new pattern using
VI12_AVX_AVX512F iterators without masking.
gcc/testsuite/
* gcc.target/i386/pr67480.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228010 138bc75d-0d04-0410-961f-82ee72b054a4
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7134b02..dc7f6a7 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -410,6 +410,14 @@
[(V16SI "TARGET_AVX512F") V8SI V4SI
(V8DI "TARGET_AVX512F") V4DI V2DI])
+(define_mode_iterator VI48_AVX_AVX512F
+ [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI
+ (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI])
+
+(define_mode_iterator VI12_AVX_AVX512F
+ [ (V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI
+ (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI])
+
(define_mode_iterator V48_AVX2
[V4SF V2DF
V8SF V4DF
@@ -10917,10 +10925,10 @@
})
(define_insn "<mask_codefor><code><mode>3<mask_name>"
- [(set (match_operand:VI 0 "register_operand" "=x,v")
- (any_logic:VI
- (match_operand:VI 1 "nonimmediate_operand" "%0,v")
- (match_operand:VI 2 "nonimmediate_operand" "xm,vm")))]
+ [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,v")
+ (any_logic:VI48_AVX_AVX512F
+ (match_operand:VI48_AVX_AVX512F 1 "nonimmediate_operand" "%0,v")
+ (match_operand:VI48_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))]
"TARGET_SSE && <mask_mode512bit_condition>
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
@@ -10949,24 +10957,120 @@
case V4DImode:
case V4SImode:
case V2DImode:
- if (TARGET_AVX512VL)
+ tmp = TARGET_AVX512VL ? "p<logic><ssemodesuffix>" : "p<logic>";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ break;
+
+ case MODE_V8SF:
+ gcc_assert (TARGET_AVX);
+ case MODE_V4SF:
+ gcc_assert (TARGET_SSE);
+ gcc_assert (!<mask_applied>);
+ tmp = "<logic>ps";
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ switch (which_alternative)
+ {
+ case 0:
+ if (<mask_applied>)
+ ops = "v%s\t{%%2, %%0, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%0, %%2}";
+ else
+ ops = "%s\t{%%2, %%0|%%0, %%2}";
+ break;
+ case 1:
+ ops = "v%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ snprintf (buf, sizeof (buf), ops, tmp);
+ return buf;
+}
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog")
+ (set (attr "prefix_data16")
+ (if_then_else
+ (and (eq_attr "alternative" "0")
+ (eq_attr "mode" "TI"))
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "<mask_prefix3>")
+ (set (attr "mode")
+ (cond [(and (match_test "<MODE_SIZE> == 16")
+ (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL"))
+ (const_string "<ssePSmode>")
+ (match_test "TARGET_AVX2")
+ (const_string "<sseinsnmode>")
+ (match_test "TARGET_AVX")
+ (if_then_else
+ (match_test "<MODE_SIZE> > 16")
+ (const_string "V8SF")
+ (const_string "<sseinsnmode>"))
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
+ (const_string "<sseinsnmode>")))])
+
+(define_insn "*<code><mode>3"
+ [(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,v")
+ (any_logic: VI12_AVX_AVX512F
+ (match_operand:VI12_AVX_AVX512F 1 "nonimmediate_operand" "%0,v")
+ (match_operand:VI12_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))]
+ "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
+{
+ static char buf[64];
+ const char *ops;
+ const char *tmp;
+ const char *ssesuffix;
+
+ switch (get_attr_mode (insn))
+ {
+ case MODE_XI:
+ gcc_assert (TARGET_AVX512F);
+ case MODE_OI:
+ gcc_assert (TARGET_AVX2 || TARGET_AVX512VL);
+ case MODE_TI:
+ gcc_assert (TARGET_SSE2 || TARGET_AVX512VL);
+ switch (<MODE>mode)
+ {
+ case V64QImode:
+ case V32HImode:
+ if (TARGET_AVX512F)
{
- tmp = "p<logic><ssemodesuffix>";
+ tmp = "p<logic>";
+ ssesuffix = "q";
+ break;
+ }
+ case V32QImode:
+ case V16HImode:
+ case V16QImode:
+ case V8HImode:
+ if (TARGET_AVX512VL || TARGET_AVX2 || TARGET_SSE2)
+ {
+ tmp = "p<logic>";
+ ssesuffix = TARGET_AVX512VL ? "q" : "";
break;
}
default:
- tmp = TARGET_AVX512VL ? "p<logic>q" : "p<logic>";
+ gcc_unreachable ();
}
break;
- case MODE_V16SF:
- gcc_assert (TARGET_AVX512F);
case MODE_V8SF:
gcc_assert (TARGET_AVX);
case MODE_V4SF:
gcc_assert (TARGET_SSE);
-
tmp = "<logic>ps";
+ ssesuffix = "";
break;
default:
@@ -10977,15 +11081,16 @@
{
case 0:
ops = "%s\t{%%2, %%0|%%0, %%2}";
+ snprintf (buf, sizeof (buf), ops, tmp);
break;
case 1:
- ops = "v%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
+ ops = "v%s%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
+ snprintf (buf, sizeof (buf), ops, tmp, ssesuffix);
break;
default:
gcc_unreachable ();
}
- snprintf (buf, sizeof (buf), ops, tmp);
return buf;
}
[(set_attr "isa" "noavx,avx")
diff --git a/gcc/testsuite/gcc.target/i386/pr67480.c b/gcc/testsuite/gcc.target/i386/pr67480.c
new file mode 100644
index 0000000..90e6a6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr67480.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512bw -O2 -ftree-vectorize" { target i?86-*-* x86_64-*-* } } */
+
+void
+foo(const char *in, char *out, unsigned n)
+{
+ unsigned i;
+ for (i = 0; i < n; i++)
+ out[i] &= in[i];
+}
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
2015-10-06 12:10 ` Kirill Yukhin
@ 2015-10-08 5:14 ` Kirill Yukhin
2015-10-08 7:02 ` Uros Bizjak
0 siblings, 1 reply; 9+ messages in thread
From: Kirill Yukhin @ 2015-10-08 5:14 UTC (permalink / raw)
To: H.J. Lu; +Cc: Uros Bizjak, GCC Patches
Hello,
On 06 Oct 15:09, Kirill Yukhin wrote:
> > > This caused:
> > >
> > > FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
> > >
> > > on gcc-5-branch.
> > >
> >
> > vect-perm-odd-1.s: Assembler messages:
> > vect-perm-odd-1.s:233: Error: operand type mismatch for `vpor'
> > vect-perm-odd-1.s:240: Error: operand type mismatch for `vpor'
> >
> > vpor %zmm1, %zmm2, %zmm1
> >
> > It should be
> >
> > vporq %zmm1, %zmm2, %zmm1
>
> It looks like patch revealed issue w/ wrong `or' emit.
> Patch of Alexander Fomin fixes it.
>
> I've backported it for gcc-5.
>
> Bootstrapped. Regtest in progress.
> Is it ok for gcc-5 if regtesting pass?
Regtesting pass.
Is it ok for gcc-5-branch?
--
Thanks, K
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
2015-10-08 5:14 ` Kirill Yukhin
@ 2015-10-08 7:02 ` Uros Bizjak
0 siblings, 0 replies; 9+ messages in thread
From: Uros Bizjak @ 2015-10-08 7:02 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: H.J. Lu, GCC Patches
On Thu, Oct 8, 2015 at 7:14 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
> On 06 Oct 15:09, Kirill Yukhin wrote:
>> > > This caused:
>> > >
>> > > FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
>> > >
>> > > on gcc-5-branch.
>> > >
>> >
>> > vect-perm-odd-1.s: Assembler messages:
>> > vect-perm-odd-1.s:233: Error: operand type mismatch for `vpor'
>> > vect-perm-odd-1.s:240: Error: operand type mismatch for `vpor'
>> >
>> > vpor %zmm1, %zmm2, %zmm1
>> >
>> > It should be
>> >
>> > vporq %zmm1, %zmm2, %zmm1
>>
>> It looks like patch revealed issue w/ wrong `or' emit.
>> Patch of Alexander Fomin fixes it.
>>
>> I've backported it for gcc-5.
>>
>> Bootstrapped. Regtest in progress.
>> Is it ok for gcc-5 if regtesting pass?
> Regtesting pass.
>
> Is it ok for gcc-5-branch?
+/* { dg-options "-mavx512bw -O2 -ftree-vectorize" { target i?86-*-*
x86_64-*-* } } */
No need for target selector in gcc.target/i386 directory.
OK.
Thanks,
Uros.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
2015-10-03 10:49 Dominique d'Humières
@ 2015-10-04 14:04 ` Uros Bizjak
0 siblings, 0 replies; 9+ messages in thread
From: Uros Bizjak @ 2015-10-04 14:04 UTC (permalink / raw)
To: Dominique d'Humières; +Cc: Kirill Yukhin, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 2209 bytes --]
On Sat, Oct 3, 2015 at 12:49 PM, Dominique d'Humières
<dominiq@lps.ens.fr> wrote:
> Kirill,
>
> The new tests fail on x86_64-apple-darwin14:
>
> FAIL: gcc.target/i386/vect-pack-trunc-1.c (test for excess errors)
> UNRESOLVED: gcc.target/i386/vect-pack-trunc-1.c compilation failed to produce executable
> FAIL: gcc.target/i386/vect-pack-trunc-2.c (test for excess errors)
> UNRESOLVED: gcc.target/i386/vect-pack-trunc-2.c compilation failed to produce executable
> FAIL: gcc.target/i386/vect-perm-even-1.c (test for excess errors)
> UNRESOLVED: gcc.target/i386/vect-perm-even-1.c compilation failed to produce executable
> FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
> UNRESOLVED: gcc.target/i386/vect-perm-odd-1.c compilation failed to produce executable
> FAIL: gcc.target/i386/vect-unpack-1.c (test for excess errors)
> UNRESOLVED: gcc.target/i386/vect-unpack-1.c compilation failed to produce executable
> FAIL: gcc.target/i386/vect-unpack-2.c (test for excess errors)
> UNRESOLVED: gcc.target/i386/vect-unpack-2.c compilation failed to produce executable
>
> I think the tests should be protected with
>
> /* { dg-require-effective-target avx512bw } */
You are correct. Fixed by attached patch.
2015-10-04 Uros Bizjak <ubizjak@gmail.com>
* gcc.target/i386/vect-pack-trunc-1.c: Require avx512bw
effective target.
* gcc.target/i386/vect-pack-trunc-2.c: Ditto.
* gcc.target/i386/vect-perm-even-1.c: Ditto.
* gcc.target/i386/vect-perm-odd-1.c: Ditto.
* gcc.target/i386/vect-unpack-1.c: Ditto.
* gcc.target/i386/vect-unpack-2.c: Ditto.
Tested on x86_64-linux-gnu {,-m32} and committed to mainline SVN.
> Note also that the options '-fno-diagnostics-show-caret -fdiagnostics-color=never -O2’ are not obeyed:
>
> ^[[1mvect-pack-trunc-1.s:67:2: ^[[0;1;31merror: ^[[0m^[[1minstruction requires: AVX-512 ISA
> ^[[0m vmovdqa64 LC0-L1$pb(%ebx), %zmm0
> ^[[0;1;32m ^
> ^[[0m^[[1mvect-pack-trunc-1.s:68:2: ^[[0;1;31merror: ^[[0m^[[1minstruction requires: AVX-512 ISA
> ^[[0m vmovdqa64 LC1-L1$pb(%ebx), %zmm4
> ^[[0;1;32m ^
This error is not from the compiler.
Uros.
[-- Attachment #2: t.diff.txt --]
[-- Type: text/plain, Size: 2499 bytes --]
Index: gcc.target/i386/vect-pack-trunc-1.c
===================================================================
--- gcc.target/i386/vect-pack-trunc-1.c (revision 228455)
+++ gcc.target/i386/vect-pack-trunc-1.c (working copy)
@@ -1,5 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+/* { dg-require-effective-target avx512bw } */
#include "avx512bw-check.h"
Index: gcc.target/i386/vect-pack-trunc-2.c
===================================================================
--- gcc.target/i386/vect-pack-trunc-2.c (revision 228455)
+++ gcc.target/i386/vect-pack-trunc-2.c (working copy)
@@ -1,5 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+/* { dg-require-effective-target avx512bw } */
#include "avx512bw-check.h"
Index: gcc.target/i386/vect-perm-even-1.c
===================================================================
--- gcc.target/i386/vect-perm-even-1.c (revision 228455)
+++ gcc.target/i386/vect-perm-even-1.c (working copy)
@@ -1,5 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+/* { dg-require-effective-target avx512bw } */
#include "avx512bw-check.h"
Index: gcc.target/i386/vect-perm-odd-1.c
===================================================================
--- gcc.target/i386/vect-perm-odd-1.c (revision 228455)
+++ gcc.target/i386/vect-perm-odd-1.c (working copy)
@@ -1,5 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+/* { dg-require-effective-target avx512bw } */
#include "avx512bw-check.h"
Index: gcc.target/i386/vect-unpack-1.c
===================================================================
--- gcc.target/i386/vect-unpack-1.c (revision 228455)
+++ gcc.target/i386/vect-unpack-1.c (working copy)
@@ -1,5 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+/* { dg-require-effective-target avx512bw } */
#include "avx512bw-check.h"
Index: gcc.target/i386/vect-unpack-2.c
===================================================================
--- gcc.target/i386/vect-unpack-2.c (revision 228455)
+++ gcc.target/i386/vect-unpack-2.c (working copy)
@@ -1,5 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2 -ftree-vectorize -ffast-math -mavx512bw -save-temps" } */
+/* { dg-require-effective-target avx512bw } */
#include "avx512bw-check.h"
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns.
@ 2015-10-03 10:49 Dominique d'Humières
2015-10-04 14:04 ` Uros Bizjak
0 siblings, 1 reply; 9+ messages in thread
From: Dominique d'Humières @ 2015-10-03 10:49 UTC (permalink / raw)
To: kirill.yukhin; +Cc: ubizjak, GCC Patches
Kirill,
The new tests fail on x86_64-apple-darwin14:
FAIL: gcc.target/i386/vect-pack-trunc-1.c (test for excess errors)
UNRESOLVED: gcc.target/i386/vect-pack-trunc-1.c compilation failed to produce executable
FAIL: gcc.target/i386/vect-pack-trunc-2.c (test for excess errors)
UNRESOLVED: gcc.target/i386/vect-pack-trunc-2.c compilation failed to produce executable
FAIL: gcc.target/i386/vect-perm-even-1.c (test for excess errors)
UNRESOLVED: gcc.target/i386/vect-perm-even-1.c compilation failed to produce executable
FAIL: gcc.target/i386/vect-perm-odd-1.c (test for excess errors)
UNRESOLVED: gcc.target/i386/vect-perm-odd-1.c compilation failed to produce executable
FAIL: gcc.target/i386/vect-unpack-1.c (test for excess errors)
UNRESOLVED: gcc.target/i386/vect-unpack-1.c compilation failed to produce executable
FAIL: gcc.target/i386/vect-unpack-2.c (test for excess errors)
UNRESOLVED: gcc.target/i386/vect-unpack-2.c compilation failed to produce executable
I think the tests should be protected with
/* { dg-require-effective-target avx512bw } */
Note also that the options '-fno-diagnostics-show-caret -fdiagnostics-color=never -O2’ are not obeyed:
^[[1mvect-pack-trunc-1.s:67:2: ^[[0;1;31merror: ^[[0m^[[1minstruction requires: AVX-512 ISA
^[[0m vmovdqa64 LC0-L1$pb(%ebx), %zmm0
^[[0;1;32m ^
^[[0m^[[1mvect-pack-trunc-1.s:68:2: ^[[0;1;31merror: ^[[0m^[[1minstruction requires: AVX-512 ISA
^[[0m vmovdqa64 LC1-L1$pb(%ebx), %zmm4
^[[0;1;32m ^
…
Dominique
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-10-08 7:02 UTC | newest]
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-- links below jump to the message on this page --
2015-10-01 11:12 [PATCH, i386, AVX-512] Update extract_even_odd w/ AVX-512BW insns Kirill Yukhin
2015-10-02 14:38 ` Kirill Yukhin
2015-10-06 11:05 ` H.J. Lu
2015-10-06 11:18 ` H.J. Lu
2015-10-06 12:10 ` Kirill Yukhin
2015-10-08 5:14 ` Kirill Yukhin
2015-10-08 7:02 ` Uros Bizjak
2015-10-03 10:49 Dominique d'Humières
2015-10-04 14:04 ` Uros Bizjak
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