From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 108892 invoked by alias); 1 Oct 2015 14:51:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 108825 invoked by uid 89); 1 Oct 2015 14:51:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-io0-f170.google.com Received: from mail-io0-f170.google.com (HELO mail-io0-f170.google.com) (209.85.223.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 01 Oct 2015 14:51:36 +0000 Received: by iofh134 with SMTP id h134so88206762iof.0 for ; Thu, 01 Oct 2015 07:51:34 -0700 (PDT) X-Received: by 10.107.11.154 with SMTP id 26mr12944501iol.105.1443711094457; Thu, 01 Oct 2015 07:51:34 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr01-ext.jf.intel.com. [134.134.139.70]) by smtp.gmail.com with ESMTPSA id i26sm2823746iod.27.2015.10.01.07.51.31 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Oct 2015 07:51:33 -0700 (PDT) Date: Thu, 01 Oct 2015 14:51:00 -0000 From: Kirill Yukhin To: Uros Bizjak Cc: GCC Patches Subject: [PATCH, i386, AVX-512, doc] Mention all AVX-512 switches in invoke.texi. Message-ID: <20151001145114.GB17847@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg00082.txt.bz2 Hello, This patch adds missing AVX-512 switches to invoke.texi. `make pdf` looks ok. Is it ok for trunk and gcc-5-branch (a week after check in to trunk)? gcc/ * doc/invoke.texi: Mention -mavx512vl, -mavx512bw, -mavx512dq, -mavx521vbmi, -mavx512ifma. Add missing opindex-es. -- Thanks, K commit 5615034caed821c52f0a8c97966e0160f6dd9a5e Author: Kirill Yukhin Date: Thu Oct 1 16:57:52 2015 +0300 AVX-512. Mention all AVX-512 switches in invoke.texi. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ebfaaa1..b5f4b81 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1085,9 +1085,10 @@ See RS/6000 and PowerPC Options. -mrecip -mrecip=@var{opt} @gol -mvzeroupper -mprefer-avx128 @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol --mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -msha @gol --maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma -mprefetchwt1 @gol --mclflushopt -mxsavec -mxsaves @gol +-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -mavx512vl @gol +-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol +-mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol +-mprefetchwt1 -mclflushopt -mxsavec -mxsaves @gol -msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol -mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx -mthreads @gol -mno-align-stringops -minline-all-stringops @gol @@ -22810,31 +22811,58 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex msse @need 200 @itemx -msse2 +@opindex msse2 @need 200 @itemx -msse3 +@opindex msse3 @need 200 @itemx -mssse3 +@opindex mssse3 @need 200 @itemx -msse4 +@opindex msse4 @need 200 @itemx -msse4a +@opindex msse4a @need 200 @itemx -msse4.1 +@opindex msse4.1 @need 200 @itemx -msse4.2 +@opindex msse4.2 @need 200 @itemx -mavx @opindex mavx @need 200 @itemx -mavx2 +@opindex mavx2 @need 200 @itemx -mavx512f +@opindex mavx512f @need 200 @itemx -mavx512pf +@opindex mavx512pf @need 200 @itemx -mavx512er +@opindex mavx512er @need 200 @itemx -mavx512cd +@opindex mavx512cd +@need 200 +@itemx -mavx512vl +@opindex mavx512vl +@need 200 +@itemx -mavx512bw +@opindex mavx512bw +@need 200 +@itemx -mavx512dq +@opindex mavx512dq +@need 200 +@itemx -mavx512ifma +@opindex mavx512ifma +@need 200 +@itemx -mavx512vbmi +@opindex mavx512vbmi @need 200 @itemx -msha @opindex msha @@ -22861,8 +22889,10 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex mfma @need 200 @itemx -mfma4 +@opindex mfma4 @need 200 @itemx -mno-fma4 +@opindex mno-fma4 @need 200 @itemx -mprefetchwt1 @opindex mprefetchwt1 @@ -22919,7 +22949,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, -BMI, BMI2, FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX or 3DNow!@: +AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR, +XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX or 3DNow!@: extended instruction sets. Each has a corresponding @option{-mno-} option to disable use of these instructions.