From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 99874 invoked by alias); 8 Oct 2015 15:42:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 99862 invoked by uid 89); 8 Oct 2015 15:42:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ig0-f172.google.com Received: from mail-ig0-f172.google.com (HELO mail-ig0-f172.google.com) (209.85.213.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 08 Oct 2015 15:42:57 +0000 Received: by igbkq10 with SMTP id kq10so15752606igb.0 for ; Thu, 08 Oct 2015 08:42:55 -0700 (PDT) X-Received: by 10.50.62.46 with SMTP id v14mr4659282igr.79.1444318975088; Thu, 08 Oct 2015 08:42:55 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by smtp.gmail.com with ESMTPSA id o9sm3765309igh.5.2015.10.08.08.42.53 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Oct 2015 08:42:54 -0700 (PDT) Date: Thu, 08 Oct 2015 15:42:00 -0000 From: Ilya Enkovich To: gcc-patches@gcc.gnu.org Subject: [mask-load, patch 2/2, i386] Add/modify mask load/store patterns Message-ID: <20151008154227.GI63757@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg00860.txt.bz2 Hi, This patch reflects changes in maskload and maskstore optabs and adds patterns for AVX-512. Thanks, Ilya -- 2015-10-08 Ilya Enkovich * config/i386/sse.md (maskload): Rename to ... (maskload): ... this. (maskstore): Rename to ... (maskstore): ... this. (maskload): New. (maskstore): New. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3a9d2d3..48424fc 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -18153,7 +18153,7 @@ (set_attr "btver2_decode" "vector") (set_attr "mode" "")]) -(define_expand "maskload" +(define_expand "maskload" [(set (match_operand:V48_AVX2 0 "register_operand") (unspec:V48_AVX2 [(match_operand: 2 "register_operand") @@ -18161,7 +18161,23 @@ UNSPEC_MASKMOV))] "TARGET_AVX") -(define_expand "maskstore" +(define_expand "maskload" + [(set (match_operand:V48_AVX512VL 0 "register_operand") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "memory_operand") + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512F") + +(define_expand "maskload" + [(set (match_operand:VI12_AVX512VL 0 "register_operand") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "memory_operand") + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512BW") + +(define_expand "maskstore" [(set (match_operand:V48_AVX2 0 "memory_operand") (unspec:V48_AVX2 [(match_operand: 2 "register_operand") @@ -18170,6 +18186,22 @@ UNSPEC_MASKMOV))] "TARGET_AVX") +(define_expand "maskstore" + [(set (match_operand:V48_AVX512VL 0 "memory_operand") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "register_operand") + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512F") + +(define_expand "maskstore" + [(set (match_operand:VI12_AVX512VL 0 "memory_operand") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "register_operand") + (match_dup 0) + (match_operand: 2 "register_operand")))] + "TARGET_AVX512BW") + (define_insn_and_split "avx__" [(set (match_operand:AVX256MODE2P 0 "nonimmediate_operand" "=x,m") (unspec:AVX256MODE2P