From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 35611 invoked by alias); 8 Oct 2015 15:55:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 34670 invoked by uid 89); 8 Oct 2015 15:54:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qg0-f47.google.com Received: from mail-qg0-f47.google.com (HELO mail-qg0-f47.google.com) (209.85.192.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 08 Oct 2015 15:54:58 +0000 Received: by qgx61 with SMTP id 61so45581388qgx.3 for ; Thu, 08 Oct 2015 08:54:55 -0700 (PDT) X-Received: by 10.140.152.85 with SMTP id 82mr10054623qhy.8.1444319695822; Thu, 08 Oct 2015 08:54:55 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by smtp.gmail.com with ESMTPSA id 42sm14681794qky.39.2015.10.08.08.54.53 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Oct 2015 08:54:55 -0700 (PDT) Date: Thu, 08 Oct 2015 15:55:00 -0000 From: Ilya Enkovich To: gcc-patches@gcc.gnu.org Subject: [mask-vec_cond, patch 2/2, i386] Add patterns for vcond_mask_optab Message-ID: <20151008155324.GK63757@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg00863.txt.bz2 Hi, This patch add patterns for vcond_mask_optab. No new expand code is required, existing ix86_expand_sse_movcc is used. Thanks, Ilya -- gcc/ChangeLog: 2015-10-08 Ilya Enkovich * config/i386/i386-protos.h (ix86_expand_sse_movcc): New. * config/i386/i386.c (ix86_expand_sse_movcc): Make public. Cast mask to FP mode if required. * config/i386/sse.md (vcond_mask_): New. (vcond_mask_): New. (vcond_mask_): New. (vcond_mask_): New. (vcond_mask_v2div2di): New. (vcond_mask_): New. (vcond_mask_): New. diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index e22aa57..6a0e437 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -132,6 +132,7 @@ extern bool ix86_expand_vec_perm_const (rtx[]); extern bool ix86_expand_mask_vec_cmp (rtx[]); extern bool ix86_expand_int_vec_cmp (rtx[]); extern bool ix86_expand_fp_vec_cmp (rtx[]); +extern void ix86_expand_sse_movcc (rtx, rtx, rtx, rtx); extern void ix86_expand_sse_unpack (rtx, rtx, bool, bool); extern bool ix86_expand_int_addcc (rtx[]); extern rtx ix86_expand_call (rtx, rtx, rtx, rtx, rtx, bool); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index a8e3538..0619b9a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -21497,7 +21497,7 @@ ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1, /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical operations. This is used for both scalar and vector conditional moves. */ -static void +void ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) { machine_mode mode = GET_MODE (dest); diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 48424fc..1e5a455 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3015,6 +3015,87 @@ DONE; }) +(define_expand "vcond_mask_" + [(set (match_operand:V48_AVX512VL 0 "register_operand") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 1 "nonimmediate_operand") + (match_operand:V48_AVX512VL 2 "vector_move_operand") + (match_operand: 3 "register_operand")))] + "TARGET_AVX512F") + +(define_expand "vcond_mask_" + [(set (match_operand:VI12_AVX512VL 0 "register_operand") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "nonimmediate_operand") + (match_operand:VI12_AVX512VL 2 "vector_move_operand") + (match_operand: 3 "register_operand")))] + "TARGET_AVX512BW") + +(define_expand "vcond_mask_" + [(set (match_operand:VI_256 0 "register_operand") + (vec_merge:VI_256 + (match_operand:VI_256 1 "nonimmediate_operand") + (match_operand:VI_256 2 "vector_move_operand") + (match_operand: 3 "register_operand")))] + "TARGET_AVX2" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_" + [(set (match_operand:VI124_128 0 "register_operand") + (vec_merge:VI124_128 + (match_operand:VI124_128 1 "nonimmediate_operand") + (match_operand:VI124_128 2 "vector_move_operand") + (match_operand: 3 "register_operand")))] + "TARGET_SSE2" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_v2div2di" + [(set (match_operand:V2DI 0 "register_operand") + (vec_merge:V2DI + (match_operand:V2DI 1 "nonimmediate_operand") + (match_operand:V2DI 2 "vector_move_operand") + (match_operand:V2DI 3 "register_operand")))] + "TARGET_SSE4_2" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_" + [(set (match_operand:VF_256 0 "register_operand") + (vec_merge:VF_256 + (match_operand:VF_256 1 "nonimmediate_operand") + (match_operand:VF_256 2 "vector_move_operand") + (match_operand: 3 "register_operand")))] + "TARGET_AVX" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + +(define_expand "vcond_mask_" + [(set (match_operand:VF_128 0 "register_operand") + (vec_merge:VF_128 + (match_operand:VF_128 1 "nonimmediate_operand") + (match_operand:VF_128 2 "vector_move_operand") + (match_operand: 3 "register_operand")))] + "TARGET_SSE" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel floating point logical operations