From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 115400 invoked by alias); 28 Oct 2015 09:51:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 115372 invoked by uid 89); 28 Oct 2015 09:51:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 28 Oct 2015 09:51:42 +0000 Received: from arm.com (e107456-lin.cambridge.arm.com [10.2.206.78]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id t9S9pc3h013489; Wed, 28 Oct 2015 09:51:38 GMT Date: Wed, 28 Oct 2015 10:07:00 -0000 From: James Greenhalgh To: Kyrill Tkachov Cc: GCC Patches , Marcus Shawcroft , Richard Earnshaw Subject: Re: [PATCH][AArch64] PR 68102: Check that operand is REG before checking the REGNO in mov-immediate splitters Message-ID: <20151028095137.GA33627@arm.com> References: <562FBD14.3050105@arm.com> <20151027182623.GA5222@arm.com> <56309A47.2030509@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <56309A47.2030509@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg03009.txt.bz2 On Wed, Oct 28, 2015 at 09:49:59AM +0000, Kyrill Tkachov wrote: > Hi James, > > On 27/10/15 18:26, James Greenhalgh wrote: > >On Tue, Oct 27, 2015 at 06:06:12PM +0000, Kyrill Tkachov wrote: > >>Hi all, > >> > >>This is another RTL checking error occuring in the splitting condition of the > >>mov-immediate patterns. We take a REGNO of operands[0] which is a > >>nonimmediate_operand. Since the immediate splitting code only makes sense > >>when the destination is a register, we should be guarding that condition on > >>REG_P (operands[0]). > >> > >>The reported error occurs on the *movdi_aarch64 pattern but I see the same > >>vulnerability in the *movsi_aarch64 pattern, although I wasn't able to get it > >>to trigger an ICE. > >> > >>This patch adds a REG_P check on the splitting condition of both. The > >>testcase (taken from the BZ for PR 68102 and with an #if 1 removed)now > >>compiles fine on an aarch64 compiler with RTL checking enabled. > >>Bootstrapped and tested on aarch64-linux with RTL checking enabled. > >> > >>Ok for trunk? > >OK. > > > >>Thanks, > >>Kyrill > >> > >>The BZ says this occurs on the GCC 5 branch but I don't have a checking > >>compiler from that branch yet. I'll be investigating whether to backport this > >>patch there in the meantime. > >Sounds good to me. > > So I reproduced the checking ICE on the GCC 5 and the patch applies > cleanly there and fixes it. > > So ok to commit it there after a bootstrap and test on that branch? Yes, please. Thanks, James