Re: [PATCH 1/4][AArch64] Add scheduling and cost models for Exynos M1

[James Greenhalgh <james.greenhalgh@arm.com>]

On Wed, Nov 04, 2015 at 05:21:03PM -0600, Evandro Menezes wrote:
> Please, ignore the previous patch.  This is the intended patch.
> 
> Sorry.
> 
> -- 
> Evandro Menezes
> 
> On 11/04/2015 05:18 PM, Evandro Menezes wrote:
> >This patch adds extra tuning information about AArch64 targets:
> >
> > * Maximum number of case values before resorting to a jump table
> >   The default values assumed independently of the specific backends
> >   may be rather low for modern processors, which sport quite efficient
> >   direct branch prediction, whereas indirect branch prediction is
> >   still typically not so efficient.  This value may be specifically
> >   set for a processor or left at zero to use the default values.
> > * L1 cache line size
> >   The auto-prefetcher uses this information when emitting software
> >   prefetch insns.
> >
> >Please, commit if it's alright.
> >
> >Thank you,
> >
> 

Thanks for the patch,

> diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
> index 81792bc..ecf4685 100644
> --- a/gcc/config/aarch64/aarch64-protos.h
> +++ b/gcc/config/aarch64/aarch64-protos.h
> @@ -195,6 +195,9 @@ struct tune_params
>    int vec_reassoc_width;
>    int min_div_recip_mul_sf;
>    int min_div_recip_mul_df;
> +  int max_case_values; /* Case values threshold; or 0 for the default.  */

If we're using an int, how about -1 as the sentinel value? (Maybe someone
really likes jump tables!). Otherwise, make this an unsigned int?

> +
> +  int cache_line_size; /* Cache line size; or 0 for the default.  */

unsigned int?

The patch is otherwise OK, though it needs a ChangeLog.

Thanks,
James