From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 66802 invoked by alias); 10 Nov 2015 21:56:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 66738 invoked by uid 89); 10 Nov 2015 21:56:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.3 required=5.0 tests=AWL,BAYES_40,KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 X-HELO: e38.co.us.ibm.com Received: from e38.co.us.ibm.com (HELO e38.co.us.ibm.com) (32.97.110.159) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Tue, 10 Nov 2015 21:56:21 +0000 Received: from localhost by e38.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 10 Nov 2015 14:56:18 -0700 X-IBM-Helo: d03dlp01.boulder.ibm.com X-IBM-MailFrom: meissner@ibm-tiger.the-meissners.org X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 148B81FF0041 for ; Tue, 10 Nov 2015 14:44:29 -0700 (MST) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tAALt5T19830852 for ; Tue, 10 Nov 2015 14:55:06 -0700 Received: from d03av02.boulder.ibm.com (localhost [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tAALuGTo025742 for ; Tue, 10 Nov 2015 14:56:16 -0700 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-111.usma.ibm.com [9.32.77.111]) by d03av02.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id tAALuGsr025683; Tue, 10 Nov 2015 14:56:16 -0700 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id C976A42CCD; Tue, 10 Nov 2015 16:56:15 -0500 (EST) Date: Tue, 10 Nov 2015 21:56:00 -0000 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: Re: [PATCH], Add power9 support to GCC, patch #10 (SFmode/DFmode d-form addressing) Message-ID: <20151110215615.GA26545@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com References: <20151103202911.GA5304@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20151103202911.GA5304@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15111021-0029-0000-0000-00000E0813FB X-IsSubscribed: yes X-SW-Source: 2015-11/txt/msg01293.txt.bz2 This patch d-form addressing to float/double scalars for the PowerPC that was added in ISA 3.0 (power9). This patch does not yet turn on D-form addressing as default. It is likely that patch #11, which will add limited d-form addressing to vector registers will enable it by default. I have bootstrapped the compiler with these changes, and there were no regressions to the testsuite. In addition, I built all of the Spec 2006 benchmark with my normal options (-ffast-math -O3 -mveclibabi=mass -mcpu=power9 -mpower9-dform -mrecip=rsqrt -fpeel-loops -funroll-loops -fvect-cost-model -msave-toc-indirect -fno-aggressive-loop-optimizations -mno-pointers-to-nested-functions) and there were no compiler failures (and various power9 instructions were generated, including d-form addressing). Are these patches ok to check in? [gcc] 2015-11-10 Michael Meissner * config/rs6000/constraints.md (wb constraint): New constraint for ISA 3.0 d-form scalar addressing. * config/rs6000/rs6000.c (mode_supports_vmx_dform): Add support for ISA 3.0 D-form addressing to load SFmode/DFmode scalars into Altivec registers. Add wb constraint for Altivec registers with D-form addressing. If we have ISA 3.0 d-form support, undo secondary reload support for using FPR registers if we want to do D-form addressing. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_secondary_reload): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wb constraint. * config/rs6000/rs6000.md (f32_lr2 mode attribute): Add support for ISA 3.0 SFmode/DFmode d-form addressing to Altivec registers. (f32_lm2): Likewise. (f32_li2): Likewise. (f32_sr2): Likewise. (f32_sm2): Likewise. (f32_si2): Likewise. (f64_p9): Likewise. (extendsfdf2_fpr): Likewise. (mov_hardfloat): Likewise. (mov_hardfloat32): Likewise. (mov_hardfloat64): Likewise. * doc/md.texi (RS/6000 constraints): Document wb constraint. Fixup we constraint documentation. [gcc/testsuite] 2015-11-10 Michael Meissner * gcc.target/powerpc/dform-1.c: New test. * gcc.target/powerpc/dform-2.c: Likewise. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797