From: James Greenhalgh <james.greenhalgh@arm.com>
To: Michael Collison <michael.collison@linaro.org>
Cc: gcc Patches <gcc-patches@gcc.gnu.org>,
Richard Biener <richard.guenther@gmail.com>
Subject: Re: [Aarch64] Use vector wide add for mixed-mode adds
Date: Sun, 22 Nov 2015 16:13:00 -0000 [thread overview]
Message-ID: <20151122154800.GC36475@arm.com> (raw)
In-Reply-To: <56404283.5070503@linaro.org>
On Sun, Nov 08, 2015 at 11:51:47PM -0700, Michael Collison wrote:
> 2015-11-06 Michael Collison <Michael.Collison@linaro.org>
> * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum)
> (aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal): New patterns
> * config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes.
> * gcc.target/aarch64/saddw-1.c: New test.
> * gcc.target/aarch64/saddw-2.c: New test.
> * gcc.target/aarch64/uaddw-1.c: New test.
> * gcc.target/aarch64/uaddw-2.c: New test.
> * gcc.target/aarch64/uaddw-3.c: New test.
> * lib/target-support.exp
> (check_effective_target_vect_widen_sum_hi_to_si_pattern):
> Add aarch64 to list of support targets.
These hunks are all OK (with the minor style comments below applied).
As we understand what's happening here, let's take the regressions below
for now and add AArch64 to the targets affected by pr68333.
> * gcc.dg/vect/slp-multitypes-4.c: Disable test for
> targets with widening adds from V8HI=>V4SI.
> * gcc.dg/vect/slp-multitypes-5.c: Ditto.
> * gcc.dg/vect/vect-125.c: Ditto.
Let's leave these for now, while we wait for pr68333.
> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
> index 65a2b6f..acb7cf0 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -2750,6 +2750,60 @@
>
> ;; <su><addsub>w<q>.
>
> +(define_expand "widen_ssum<mode>3"
> + [(set (match_operand:<VDBLW> 0 "register_operand" "")
> + (plus:<VDBLW> (sign_extend:<VDBLW> (match_operand:VQW 1 "register_operand" ""))
Split this line (more than 80 characters).
> + (match_operand:<VDBLW> 2 "register_operand" "")))]
> + "TARGET_SIMD"
> + {
> + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
> + rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
> +
> + emit_insn (gen_aarch64_saddw<mode>_internal (temp, operands[2],
> + operands[1], p));
> + emit_insn (gen_aarch64_saddw2<mode> (operands[0], temp, operands[1]));
> + DONE;
> + }
> +)
> +
> +(define_expand "widen_ssum<mode>3"
> + [(set (match_operand:<VWIDE> 0 "register_operand" "")
> + (plus:<VWIDE> (sign_extend:<VWIDE>
> + (match_operand:VD_BHSI 1 "register_operand" ""))
> + (match_operand:<VWIDE> 2 "register_operand" "")))]
> + "TARGET_SIMD"
> +{
> + emit_insn (gen_aarch64_saddw<mode> (operands[0], operands[2], operands[1]));
> + DONE;
> +})
> +
> +(define_expand "widen_usum<mode>3"
> + [(set (match_operand:<VDBLW> 0 "register_operand" "")
> + (plus:<VDBLW> (zero_extend:<VDBLW> (match_operand:VQW 1 "register_operand" ""))
Split this line (more than 80 characters).
> + (match_operand:<VDBLW> 2 "register_operand" "")))]
> + "TARGET_SIMD"
> + {
> + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
> + rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
> +
> + emit_insn (gen_aarch64_uaddw<mode>_internal (temp, operands[2],
> + operands[1], p));
> + emit_insn (gen_aarch64_uaddw2<mode> (operands[0], temp, operands[1]));
> + DONE;
> + }
> +)
> +
> +(define_expand "widen_usum<mode>3"
> + [(set (match_operand:<VWIDE> 0 "register_operand" "")
> + (plus:<VWIDE> (zero_extend:<VWIDE>
> + (match_operand:VD_BHSI 1 "register_operand" ""))
> + (match_operand:<VWIDE> 2 "register_operand" "")))]
> + "TARGET_SIMD"
> +{
> + emit_insn (gen_aarch64_uaddw<mode> (operands[0], operands[2], operands[1]));
> + DONE;
> +})
> +
> (define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>"
> [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
> (ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
> @@ -2760,6 +2814,18 @@
> [(set_attr "type" "neon_<ADDSUB:optab>_widen")]
> )
>
> +(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal"
> + [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
> + (ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
> + (ANY_EXTEND:<VWIDE>
> + (vec_select:<VHALF>
> + (match_operand:VQW 2 "register_operand" "w")
> + (match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))]
> + "TARGET_SIMD"
> + "<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
> + [(set_attr "type" "neon_<ADDSUB:optab>_widen")]
> +)
> +
> (define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal"
> [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
> (ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
> diff --git a/gcc/testsuite/gcc.target/aarch64/saddw-1.c b/gcc/testsuite/gcc.target/aarch64/saddw-1.c
> new file mode 100644
> index 0000000..9db5d00
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/saddw-1.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3" } */
> +
> +
Extra newline.
> +int
> +t6(int len, void * dummy, short * __restrict x)
> +{
> + len = len & ~31;
> + int result = 0;
> + __asm volatile ("");
> + for (int i = 0; i < len; i++)
> + result += x[i];
> + return result;
> +}
> +
> +/* { dg-final { scan-assembler "saddw" } } */
> +/* { dg-final { scan-assembler "saddw2" } } */
> +
> +
> +
Trailing newlines.
> diff --git a/gcc/testsuite/gcc.target/aarch64/saddw-2.c b/gcc/testsuite/gcc.target/aarch64/saddw-2.c
> new file mode 100644
> index 0000000..6f8c8fd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/saddw-2.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3" } */
> +
> +int
> +t6(int len, void * dummy, int * __restrict x)
> +{
> + len = len & ~31;
> + long long result = 0;
> + __asm volatile ("");
> + for (int i = 0; i < len; i++)
> + result += x[i];
> + return result;
> +}
> +
> +/* { dg-final { scan-assembler "saddw" } } */
> +/* { dg-final { scan-assembler "saddw2" } } */
> +
> +
Trailing newlines.
> diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-1.c b/gcc/testsuite/gcc.target/aarch64/uaddw-1.c
> new file mode 100644
> index 0000000..e34574f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3" } */
> +
> +
Extra newline.
> +int
> +t6(int len, void * dummy, unsigned short * __restrict x)
> +{
> + len = len & ~31;
> + unsigned int result = 0;
> + __asm volatile ("");
> + for (int i = 0; i < len; i++)
> + result += x[i];
> + return result;
> +}
> +
> +/* { dg-final { scan-assembler "uaddw" } } */
> +/* { dg-final { scan-assembler "uaddw2" } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/uaddw-3.c b/gcc/testsuite/gcc.target/aarch64/uaddw-3.c
> new file mode 100644
> index 0000000..04bc7c9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/uaddw-3.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3" } */
> +
Extra newline.
> +
> +int
> +t6(int len, void * dummy, char * __restrict x)
> +{
> + len = len & ~31;
> + unsigned short result = 0;
> + __asm volatile ("");
> + for (int i = 0; i < len; i++)
> + result += x[i];
> + return result;
> +}
> +
> +/* { dg-final { scan-assembler "uaddw" } } */
> +/* { dg-final { scan-assembler "uaddw2" } } */
> +
> +
> +
Trailing newlines.
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index b543519..46f41a1 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -3943,6 +3943,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
> } else {
> set et_vect_widen_sum_hi_to_si_pattern_saved 0
> if { [istarget powerpc*-*-*]
> + || [istarget aarch64*-*-*]
> || [istarget ia64-*-*] } {
Either line ia64 up with aarch64, or line aarch64 up with ia64.
Thanks,
James
next prev parent reply other threads:[~2015-11-22 15:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-09 6:52 Michael Collison
2015-11-22 16:13 ` James Greenhalgh [this message]
2015-11-23 2:46 ` Michael Collison
2015-11-23 9:21 ` James Greenhalgh
-- strict thread matches above, loose matches on Subject: below --
2015-11-24 9:36 Michael Collison
2015-11-24 10:58 ` James Greenhalgh
2015-09-07 8:35 Michael Collison
2015-09-17 15:52 ` James Greenhalgh
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