From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 125683 invoked by alias); 23 Nov 2015 09:15:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 125665 invoked by uid 89); 23 Nov 2015 09:15:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 23 Nov 2015 09:15:38 +0000 Received: from arm.com (e107456-lin.cambridge.arm.com [10.2.206.78]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id tAN9FYfY026390; Mon, 23 Nov 2015 09:15:34 GMT Date: Mon, 23 Nov 2015 09:21:00 -0000 From: James Greenhalgh To: Michael Collison Cc: gcc Patches , Richard Biener Subject: Re: [Aarch64] Use vector wide add for mixed-mode adds Message-ID: <20151123091533.GA7470@arm.com> References: <56404283.5070503@linaro.org> <20151122154800.GC36475@arm.com> <56526AC3.7050209@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <56526AC3.7050209@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2015-11/txt/msg02654.txt.bz2 On Sun, Nov 22, 2015 at 06:24:19PM -0700, Michael Collison wrote: > > > On 11/22/2015 8:48 AM, James Greenhalgh wrote: > >On Sun, Nov 08, 2015 at 11:51:47PM -0700, Michael Collison wrote: > >>2015-11-06 Michael Collison > >> * config/aarch64/aarch64-simd.md (widen_ssum, widen_usum) > >>(aarch64_w_internal): New patterns > >> * config/aarch64/iterators.md (Vhalf, VDBLW): New mode attributes. > >> * gcc.target/aarch64/saddw-1.c: New test. > >> * gcc.target/aarch64/saddw-2.c: New test. > >> * gcc.target/aarch64/uaddw-1.c: New test. > >> * gcc.target/aarch64/uaddw-2.c: New test. > >> * gcc.target/aarch64/uaddw-3.c: New test. > >> * lib/target-support.exp > >> (check_effective_target_vect_widen_sum_hi_to_si_pattern): > >> Add aarch64 to list of support targets. > > > >These hunks are all OK (with the minor style comments below applied). > > Okay I will update with your comments. > > > >As we understand what's happening here, let's take the regressions below > >for now and add AArch64 to the targets affected by pr68333. > > > >> * gcc.dg/vect/slp-multitypes-4.c: Disable test for > >> targets with widening adds from V8HI=>V4SI. > >> * gcc.dg/vect/slp-multitypes-5.c: Ditto. > >> * gcc.dg/vect/vect-125.c: Ditto. > >Let's leave these for now, while we wait for pr68333. > > To clarify you would like me to exclude these bits from the patch? Yes, given the direction that pr68333 is going (a bug that should be fixed, rather than an expected failure) that seems best to me. Thanks, James