From: Martin Jambor <mjambor@suse.cz>
To: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: [hsa] Fix operand and instruction types for bit-ops
Date: Mon, 23 Nov 2015 14:12:00 -0000 [thread overview]
Message-ID: <20151123140135.GC6879@virgil.suse.cz> (raw)
Hi,
I have applied the following patch tot he HSA branch to fix some
rather unexpected type requirements of the HSA finalizer we discovered
when running the target-3[34].c libgomp tests.
Thanks,
Martin
2015-11-23 Martin Jambor <mjambor@suse.cz>
* hsa-gen.c (gen_hsa_binary_operation): Make immediate operands of
bit AND, OR and XOR always unsigned integer.
(gen_hsa_ternary_atomic_for_builtin): Make bit-operations have
bit-type.
---
gcc/hsa-gen.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/gcc/hsa-gen.c b/gcc/hsa-gen.c
index 0cbf3ec..0ef27de 100644
--- a/gcc/hsa-gen.c
+++ b/gcc/hsa-gen.c
@@ -2777,6 +2777,14 @@ gen_hsa_binary_operation (int opcode, hsa_op_reg *dest,
hsa_op_immed *i = dyn_cast <hsa_op_immed *> (op2);
i->set_type (BRIG_TYPE_U32);
}
+ if ((opcode == BRIG_OPCODE_OR
+ || opcode == BRIG_OPCODE_XOR
+ || opcode == BRIG_OPCODE_AND)
+ && is_a <hsa_op_immed *> (op2))
+ {
+ hsa_op_immed *i = dyn_cast <hsa_op_immed *> (op2);
+ i->set_type (hsa_uint_for_bitsize (hsa_type_bit_size (i->m_type)));
+ }
hsa_insn_basic *insn = new hsa_insn_basic (3, opcode, dest->m_type, dest,
op1, op2);
@@ -4223,6 +4231,10 @@ gen_hsa_ternary_atomic_for_builtin (bool ret_orig,
{
case BRIG_ATOMIC_LD:
case BRIG_ATOMIC_ST:
+ case BRIG_ATOMIC_AND:
+ case BRIG_ATOMIC_OR:
+ case BRIG_ATOMIC_XOR:
+ case BRIG_ATOMIC_EXCH:
mtype = hsa_bittype_for_type (mtype);
break;
default:
--
2.6.0
reply other threads:[~2015-11-23 14:01 UTC|newest]
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