From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 85616 invoked by alias); 24 Nov 2015 18:50:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 85603 invoked by uid 89); 24 Nov 2015 18:50:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.7 required=5.0 tests=AWL,BAYES_50,KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 X-HELO: e17.ny.us.ibm.com Received: from e17.ny.us.ibm.com (HELO e17.ny.us.ibm.com) (129.33.205.207) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Tue, 24 Nov 2015 18:50:20 +0000 Received: from localhost by e17.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 24 Nov 2015 13:50:16 -0500 X-IBM-Helo: d01dlp03.pok.ibm.com X-IBM-MailFrom: meissner@ibm-tiger.the-meissners.org X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 1E828C90060 for ; Tue, 24 Nov 2015 13:38:25 -0500 (EST) Received: from d01av01.pok.ibm.com (d01av01.pok.ibm.com [9.56.224.215]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tAOIoFwP19333252 for ; Tue, 24 Nov 2015 18:50:15 GMT Received: from d01av01.pok.ibm.com (localhost [127.0.0.1]) by d01av01.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tAOIoEA9015709 for ; Tue, 24 Nov 2015 13:50:14 -0500 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-111.usma.ibm.com [9.32.77.111]) by d01av01.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id tAOIoE1h015616; Tue, 24 Nov 2015 13:50:14 -0500 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 0826C45F62; Tue, 24 Nov 2015 13:50:13 -0500 (EST) Date: Tue, 24 Nov 2015 18:51:00 -0000 From: Michael Meissner To: David Edelsohn Cc: Michael Meissner , Richard Biener , Segher Boessenkool , "William J. Schmidt" , GCC Patches Subject: Re: [PATCH] lround for PowerPC Message-ID: <20151124185013.GA8088@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , David Edelsohn , Richard Biener , Segher Boessenkool , "William J. Schmidt" , GCC Patches References: <20151123215623.GA21427@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="d6Gm4EdcadzBjdND" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15112418-0041-0000-0000-000002798EF6 X-IsSubscribed: yes X-SW-Source: 2015-11/txt/msg02944.txt.bz2 --d6Gm4EdcadzBjdND Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-length: 1558 On Mon, Nov 23, 2015 at 07:04:33PM -0500, David Edelsohn wrote: > I would prefer that you reverse the meaning of "Fv" and "Fv2". "Fv" > corresponds to VSX2 and "Fv2" corresponds to VSX, which is confusing > for anyone trying to make sense of this in the future. > > Also, the lrounddi2 pattern should use "Fv" not "wa" from my > original patch. And the ChangeLog entry should list lrounddi2. > > Okay with those changes, after the cause of the SEGV is diagnosed and fixed. I checked in the following patch. Note, the segfault is independent of the patch. I will look into it shortly. I will back port this patch to GCC 5 as we discussed. 2015-11-24 David Edelsohn Michael Meissner * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec. (Fv2): New mode attribute to be used when ISA 2.06 instructions are used on SF/DF values. (abs2_fpr): Use instead of . (nabs2_fpr): Likewise. (neg2_fpr): Likewise. (copysign3_fcpsgn): Likewise. (smax3_vsx): Likewise. (smin3_vsx): Likewise. (floatsi2_lfiwax): Likewise. (floatunssi2_lfiwz): Likewise. (fctiwz_): Likewise. (fctiwuz_): Likewise. (btrunc2): Likewise. (ceil2): Likewise. (floor2): Likewise. (xsrdpi): Add support for the lround function. (lrounddi2): Likewise. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797 --d6Gm4EdcadzBjdND Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="lround.patch03b" Content-length: 9110 Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 230768) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -77,6 +77,7 @@ (define_c_enum "unspec" UNSPEC_FRIN UNSPEC_FRIP UNSPEC_FRIZ + UNSPEC_XSRDPI UNSPEC_LD_MPIC ; load_macho_picbase UNSPEC_RELD_MPIC ; re-load_macho_picbase UNSPEC_MPIC_CORRECT ; macho_correct_pic @@ -491,8 +492,16 @@ (define_mode_attr Fvsx [(SF "sp") (DF " ; SF/DF constraint for arithmetic on traditional floating point registers (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")]) -; SF/DF constraint for arithmetic on VSX registers -(define_mode_attr Fv [(SF "wy") (DF "ws") (DI "wi")]) +; SF/DF constraint for arithmetic on VSX registers using instructions added in +; ISA 2.06 (power7). This includes instructions that normally target DF mode, +; but are used on SFmode, since internally SFmode values are kept in the DFmode +; format. +(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wi")]) + +; SF/DF constraint for arithmetic on VSX registers. This is intended to be +; used for DFmode instructions added in ISA 2.06 (power7) and SFmode +; instructions added in ISA 2.07 (power8) +(define_mode_attr Fv2 [(SF "wy") (DF "ws") (DI "wi")]) ; SF/DF constraint for arithmetic on altivec registers (define_mode_attr Fa [(SF "wu") (DF "wv")]) @@ -4344,9 +4353,9 @@ (define_expand "add3" "") (define_insn "*add3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fadd %0,%1,%2 @@ -4362,9 +4371,9 @@ (define_expand "sub3" "") (define_insn "*sub3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fsub %0,%1,%2 @@ -4380,9 +4389,9 @@ (define_expand "mul3" "") (define_insn "*mul3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fmul %0,%1,%2 @@ -4398,9 +4407,9 @@ (define_expand "div3" "") (define_insn "*div3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR && !TARGET_SIMPLE_FPU" "@ fdiv %0,%1,%2 @@ -4409,8 +4418,8 @@ (define_insn "*div3_fpr" (set_attr "fp_type" "fp_div_")]) (define_insn "sqrt2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET__FPR && !TARGET_SIMPLE_FPU && (TARGET_PPC_GPOPT || (mode == SFmode && TARGET_XILINX_FPU))" "@ @@ -4421,8 +4430,8 @@ (define_insn "sqrt2" ;; Floating point reciprocal approximation (define_insn "fre" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRES))] "TARGET_" "@ @@ -4431,8 +4440,8 @@ (define_insn "fre" [(set_attr "type" "fp")]) (define_insn "*rsqrt2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_RSQRT))] "RS6000_RECIP_HAVE_RSQRTE_P (mode)" "@ @@ -4443,8 +4452,8 @@ (define_insn "*rsqrt2" ;; Floating point comparisons (define_insn "*cmp_fpr" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y") - (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fcmpu %0,%1,%2 @@ -5500,6 +5509,27 @@ (define_insn "round2" [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_")]) +(define_insn "*xsrdpi2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_XSRDPI))] + "TARGET__FPR && TARGET_VSX" + "xsrdpi %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) + +(define_expand "lrounddi2" + [(set (match_dup 2) + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")] + UNSPEC_XSRDPI)) + (set (match_operand:DI 0 "gpc_reg_operand" "=d") + (unspec:DI [(match_dup 2)] + UNSPEC_FCTID))] + "TARGET__FPR && TARGET_VSX" +{ + operands[2] = gen_reg_rtx (mode); +}) + ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" [(set (match_operand:SI 0 "memory_operand" "=Z") @@ -12468,11 +12498,11 @@ (define_expand "fma4" "") (define_insn "*fma4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" "%,,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") - (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))] + (match_operand:SFDF 1 "gpc_reg_operand" "%,,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))] "TARGET__FPR" "@ fmadd %0,%1,%2,%3 @@ -12492,11 +12522,11 @@ (define_expand "fms4" "") (define_insn "*fms4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") - (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] "TARGET__FPR" "@ fmsub %0,%1,%2,%3 @@ -12539,12 +12569,12 @@ (define_expand "nfma4" "") (define_insn "*nfma4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") - (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] "TARGET__FPR" "@ fnmadd %0,%1,%2,%3 @@ -12565,13 +12595,13 @@ (define_expand "nfms4" "") (define_insn "*nfmssf4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",,") - (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") (neg:SFDF - (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))))] + (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))))] "TARGET__FPR" "@ fnmsub %0,%1,%2,%3 --d6Gm4EdcadzBjdND--