From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 81880 invoked by alias); 16 Dec 2015 06:50:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 81862 invoked by uid 89); 16 Dec 2015 06:50:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: e06smtp09.uk.ibm.com Received: from e06smtp09.uk.ibm.com (HELO e06smtp09.uk.ibm.com) (195.75.94.105) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Wed, 16 Dec 2015 06:50:05 +0000 Received: from localhost by e06smtp09.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 16 Dec 2015 06:49:54 -0000 X-IBM-Helo: d06dlp03.portsmouth.uk.ibm.com X-IBM-MailFrom: vogt@linux.vnet.ibm.com X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id 66A281B0805F for ; Wed, 16 Dec 2015 06:50:26 +0000 (GMT) Received: from d06av10.portsmouth.uk.ibm.com (d06av10.portsmouth.uk.ibm.com [9.149.37.251]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tBG6nsdZ8847670 for ; Wed, 16 Dec 2015 06:49:54 GMT Received: from d06av10.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av10.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tBG5nttP017937 for ; Tue, 15 Dec 2015 22:49:55 -0700 Received: from bl3ahm9f.de.ibm.com (dyn-9-152-212-91.boeblingen.de.ibm.com [9.152.212.91]) by d06av10.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id tBG5ntmM017932; Tue, 15 Dec 2015 22:49:55 -0700 Received: from dvogt by bl3ahm9f.de.ibm.com with local (Exim 4.76) (envelope-from ) id 1a95uK-0000vP-Vq; Wed, 16 Dec 2015 07:49:53 +0100 Date: Wed, 16 Dec 2015 06:50:00 -0000 From: Dominik Vogt To: gcc-patches@gcc.gnu.org Cc: Andreas Krebbel , Ulrich Weigand Subject: Re: [PATCH] S/390: Allow to use r1 to r4 as literal pool base. Message-ID: <20151216064952.GA3191@linux.vnet.ibm.com> Reply-To: vogt@linux.vnet.ibm.com Mail-Followup-To: gcc-patches@gcc.gnu.org, Andreas Krebbel , Ulrich Weigand References: <20151211165048.GA23037@linux.vnet.ibm.com> <20151214150833.1A4DACDB4@oc7340732750.ibm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="rwEMma7ioTxnRzrJ" Content-Disposition: inline In-Reply-To: <20151214150833.1A4DACDB4@oc7340732750.ibm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15121606-0037-0000-0000-000004FF8E42 X-SW-Source: 2015-12/txt/msg01555.txt.bz2 --rwEMma7ioTxnRzrJ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-length: 1011 On Mon, Dec 14, 2015 at 04:08:32PM +0100, Ulrich Weigand wrote: > Dominik Vogt wrote: > > > The attached patch enables using r1 to r4 as the literal pool base pointer if > > one of them is unused in a leaf function. The unpatched code supports only r5 > > and r13. > > I don't think that r1 is actually safe here. Note that it may be used > (unconditionally) as temp register in s390_emit_prologue in certain cases; > the upcoming split-stack code will also need to use r1 in some cases. How about the attached patch? It also allows to use r0 as the temp register if possible (needs more testing). If that's too much effort, I'm fine with limiting the original patch to r4 to r2. > r2 through r4 should be fine. [ Not sure if there will be many (any?) cases > where one of those is unused but r5 isn't, however. ] This can happen if the function only uses register pairs (__int128). Actually I'm not sure whether r2 and r4 are valid candidates. Ciao Dominik ^_^ ^_^ -- Dominik Vogt IBM Germany --rwEMma7ioTxnRzrJ Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename=0001-ChangeLog Content-length: 325 gcc/ChangeLog * config/s390/s390.c (s390_init_frame_layout): Try r4 to r1 for the literal pool pointer. (s390_get_prologue_temp_regno): New function to choose the temp_reg for the prologue. Allow to use r0 if that's safe. (s390_emit_prologue): Move code choosing the temp_reg to a separate function. Add assertions. --rwEMma7ioTxnRzrJ Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="0001-S-390-Allow-to-use-r1-to-r4-as-literal-pool-base-poi.patch" Content-length: 3773 >From 806973409adc48c8ca701d55fdbad897b0e31c78 Mon Sep 17 00:00:00 2001 From: Dominik Vogt Date: Fri, 11 Dec 2015 11:33:23 +0100 Subject: [PATCH] S/390: Allow to use r1 to r4 as literal pool base pointer. The old code only considered r5 and r13. --- gcc/config/s390/s390.c | 61 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 48 insertions(+), 13 deletions(-) diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index bc6f05b..c45b992 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -9506,6 +9506,26 @@ s390_frame_info (void) & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); } +/* Returns the register number that is used as a temp register in the prologue. + */ +static int +s390_get_prologue_temp_regno (void) +{ + if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM) + && !crtl->is_leaf + && !TARGET_TPF_PROFILING) + return RETURN_REGNUM; + if (cfun_save_high_fprs_p) + /* Needs an address register. */ + return 1; + else if (TARGET_BACKCHAIN) + /* Does not need an address register. */ + return 0; + + /* No temp register needed. */ + return -1; +} + /* Generate frame layout. Fills in register and frame data for the current function in cfun->machine. This routine can be called multiple times; it will re-do the complete frame layout every time. */ @@ -9543,10 +9563,24 @@ s390_init_frame_layout (void) as base register to avoid save/restore overhead. */ if (!base_used) cfun->machine->base_reg = NULL_RTX; - else if (crtl->is_leaf && !df_regs_ever_live_p (5)) - cfun->machine->base_reg = gen_rtx_REG (Pmode, 5); else - cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM); + { + int br = 0; + + if (crtl->is_leaf) + { + int temp_regno; + + temp_regno = s390_get_prologue_temp_regno (); + /* Prefer r5 (most likely to be free). */ + for (br = 5; + br >= 1 && (br == temp_regno || df_regs_ever_live_p (br)); + br--) + ; + } + cfun->machine->base_reg = + gen_rtx_REG (Pmode, (br > 0) ? br : BASE_REGNUM); + } s390_register_info (); s390_frame_info (); @@ -10385,19 +10419,16 @@ s390_emit_prologue (void) { rtx insn, addr; rtx temp_reg; + int temp_regno; int i; int offset; int next_fpr = 0; - /* Choose best register to use for temp use within prologue. - See below for why TPF must use the register 1. */ - - if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM) - && !crtl->is_leaf - && !TARGET_TPF_PROFILING) - temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); - else - temp_reg = gen_rtx_REG (Pmode, 1); + /* If new uses of temp_reg are introduced into the prologue, be sure to + update the conditions in s390_get_prologue_temp_regno(). Otherwise the + prologue might overwrite the literal pool pointer in r1. */ + temp_regno = s390_get_prologue_temp_regno (); + temp_reg = (temp_regno >= 0) ? gen_rtx_REG (Pmode, temp_regno) : NULL_RTX; s390_save_gprs_to_fprs (); @@ -10551,7 +10582,10 @@ s390_emit_prologue (void) /* Save incoming stack pointer into temp reg. */ if (TARGET_BACKCHAIN || next_fpr) - insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx)); + { + gcc_assert (temp_regno >= 0); + insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx)); + } /* Subtract frame size from stack pointer. */ @@ -10606,6 +10640,7 @@ s390_emit_prologue (void) if (cfun_save_high_fprs_p && next_fpr) { + gcc_assert (temp_regno >= 1); /* If the stack might be accessed through a different register we have to make sure that the stack pointer decrement is not moved below the use of the stack slots. */ -- 2.3.0 --rwEMma7ioTxnRzrJ--