From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16756 invoked by alias); 16 Dec 2015 09:54:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 16743 invoked by uid 89); 16 Dec 2015 09:54:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 16 Dec 2015 09:54:23 +0000 Received: from arm.com (e107456-lin.cambridge.arm.com [10.2.206.78]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id tBG9sJsO013767; Wed, 16 Dec 2015 09:54:19 GMT Date: Wed, 16 Dec 2015 09:54:00 -0000 From: James Greenhalgh To: Wilco Dijkstra Cc: "gcc-patches@gcc.gnu.org" , nd Subject: Re: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS Message-ID: <20151216095418.GA39374@arm.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2015-12/txt/msg01568.txt.bz2 On Tue, Dec 15, 2015 at 10:54:49AM +0000, Wilco Dijkstra wrote: > ping > > > -----Original Message----- > > From: Wilco Dijkstra [mailto:Wilco.Dijkstra@arm.com] > > Sent: 06 November 2015 20:06 > > To: 'gcc-patches@gcc.gnu.org' > > Subject: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS > > > > This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS > > hook. When the cost of GENERAL_REGS and FP_REGS is identical, the register > > allocator always uses ALL_REGS even when it has a much higher cost. The > > hook changes the class to either FP_REGS or GENERAL_REGS depending on the > > mode of the register. This results in better register allocation overall, > > fewer spills and reduced codesize - particularly in SPEC2006 gamess. > > > > GCC regression passes with several minor fixes. > > > > OK for commit? > > > > ChangeLog: > > 2015-11-06 Wilco Dijkstra > > > > * gcc/config/aarch64/aarch64.c > > (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define. > > (aarch64_ira_change_pseudo_allocno_class): New function. > > * gcc/testsuite/gcc.target/aarch64/cvtf_1.c: Build with -O2. > > * gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c > > (test_corners_sisd_di): Improve force to SIMD register. > > (test_corners_sisd_si): Likewise. > > * gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c: Build with -O2. > > * gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c: > > Remove scan-assembler check for ldr. Drop the gcc/ from the ChangeLog. > > -- > > gcc/config/aarch64/aarch64.c | 22 ++++++++++++++++++++++ > > gcc/testsuite/gcc.target/aarch64/cvtf_1.c | 2 +- > > gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c | 4 ++-- > > gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c | 2 +- > > .../gcc.target/aarch64/vect-ld1r-compile-fp.c | 1 - These testsuite changes concern me a bit, and you don't mention them beyond saying they are minor fixes... > > diff --git a/gcc/testsuite/gcc.target/aarch64/cvtf_1.c b/gcc/testsuite/gcc.target/aarch64/cvtf_1.c > > index 5f2ff81..96501db 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/cvtf_1.c > > +++ b/gcc/testsuite/gcc.target/aarch64/cvtf_1.c > > @@ -1,5 +1,5 @@ > > /* { dg-do run } */ > > -/* { dg-options "-save-temps -fno-inline -O1" } */ > > +/* { dg-options "-save-temps -fno-inline -O2" } */ This one says we have a code-gen regression at -O1 ? > > > > #define FCVTDEF(ftype,itype) \ > > void \ > > diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c > > index 363f554..8465c89 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c > > +++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c > > @@ -186,9 +186,9 @@ test_corners_sisd_di (Int64x1 b) > > { > > force_simd_di (b); > > b = b >> 63; > > + force_simd_di (b); > > b = b >> 0; > > b += b >> 65; /* { dg-warning "right shift count >= width of type" } */ > > - force_simd_di (b); This one I don't understand, but seems to say that we've decided to move b out of FP_REGS after getting it in there for b = b << 63; ? So this is another register allocator regression? > > diff --git a/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c b/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c > > index a49db3e..c5a9c52 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c > > +++ b/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c > > @@ -1,6 +1,6 @@ > > /* Test vdup_lane intrinsics work correctly. */ > > /* { dg-do run } */ > > -/* { dg-options "-O1 --save-temps" } */ > > +/* { dg-options "-O2 --save-temps" } */ Another -O1 regression ? > > > > #include > > > > diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c > > index 66e0168..4711c61 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c > > +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c > > @@ -8,6 +8,5 @@ DEF (float) > > DEF (double) > > > > /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */ > > -/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */ > > /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */ This one is fine, I don't really understand what it was hoping to catch in the first place! Could you go in to some detail about why your testsuite changes are correct? Thanks, James