From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 86520 invoked by alias); 21 Jan 2016 09:24:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 86466 invoked by uid 89); 21 Jan 2016 09:24:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.1 required=5.0 tests=AWL,BAYES_50,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=fadd, 707, 70,7, sd X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 21 Jan 2016 09:24:07 +0000 Received: from arm.com (e107456-lin.cambridge.arm.com [10.2.206.78]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id u0L9O2iD011448; Thu, 21 Jan 2016 09:24:02 GMT Date: Thu, 21 Jan 2016 09:24:00 -0000 From: James Greenhalgh To: Evandro Menezes Cc: Wilco Dijkstra , "gcc-patches@gcc.gnu.org" , nd , Andrew Pinski Subject: Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP Message-ID: <20160121092402.GA8842@arm.com> References: <568C3D19.908@samsung.com> <568D7CBF.2070407@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <568D7CBF.2070407@samsung.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2016-01/txt/msg01601.txt.bz2 On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote: > Hi, Wilco. > > On 01/06/2016 06:04 AM, Wilco Dijkstra wrote: > >>Here's what I had in mind when I inquired about distinguishing FCMP from > >>FCCMP. As you can see in the patch, Exynos is the only target that > >>cares about it, but I wonder if ThunderX or Xgene would too. > >> > >>What do you think? > >The new attributes look fine (I've got a similar outstanding change), however > >please don't add them to non-AArch64 cores. We only need it for thunderx.md, > >cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md. > > Add support for the FCCMP insn types > > 2016-01-04 Evandro Menezes > > gcc/ > * config/aarch64/aarch64.md (fccmp): Change insn type. > (fccmpe): Likewise. > * config/aarch64/thunderx.md (thunderx_fcmp): Add > "fccmp{s,d}" types. > * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise. > * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise. > * config/arm/xgene1.md (xgene1_fcmp): Likewise. > * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn > reservation. > * config/arm/types.md (fccmps): Add new insn type. > (fccmpd): Likewise. > > Got it. Here's an updated patch. Again, assuming that your > original patch is in place. Perhaps you can build on it. If we don't have any targets which care about the fccmps/fccmpd split in the code base, do we really need it? Can we just follow the example of fcsel? > diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md > index 321ff89..daf7162 100644 > --- a/gcc/config/arm/types.md > +++ b/gcc/config/arm/types.md > @@ -70,6 +70,7 @@ > ; f_rint[d,s] double/single floating point rount to integral. > ; f_store[d,s] double/single store to memory. Used for VFP unit. > ; fadd[d,s] double/single floating-point scalar addition. > +; fccmp[d,s] double/single floating-point conditional compare. Can we follow the convention fcsel uses of calling out "From ARMv8-A:" for this type? Thanks, James