[PATCH 8/9] S/390: Use define_subst for the setmem patterns.

[PATCH 8/9] S/390: Use define_subst for the setmem patterns.

[Andreas Krebbel]

While trying to get rid of the Y constraint in the setmem patterns I
noticed that for these patterns it isn't even a problem since these
always only use the constraint with a Pmode match_operand.  But while
being at it I've tried to fold some of the patterns a bit.

gcc/ChangeLog:

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/constraints.md ("jm8"): New constraint.
	* config/s390/predicates.md ("const_int_8bitset_operand"): New predicate.
	* config/s390/s390.md ("*setmem_long", "*setmem_long_and"): Merge
	into ...
	("*setmem_long<setmem_and>"): New pattern.
	("*setmem_long_31z", "*setmem_long_and_31z"): Merge
	into ...
	("*setmem_long_31z<setmem_and>"): New pattern.
	* config/s390/subst.md ("setmem_31z_subst", "setmem_and_subst"):
	New substitution rules with the required attributes.

---
 gcc/config/s390/constraints.md |  5 +++++
 gcc/config/s390/predicates.md  |  6 ++++++
 gcc/config/s390/s390.md        | 35 ++---------------------------------
 gcc/config/s390/subst.md       | 25 +++++++++++++++++++++++++
 4 files changed, 38 insertions(+), 33 deletions(-)

diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md
index 60a7edf..6eeaa98 100644
--- a/gcc/config/s390/constraints.md
+++ b/gcc/config/s390/constraints.md
@@ -37,6 +37,7 @@
 ;;         jKK: constant vector with all elements having the same value and
 ;;              matching K constraint
 ;;         jm6: An integer operand with the lowest order 6 bits all ones.
+;;         jm8: An integer operand with the lowest order 8 bits all ones.
 ;;    t -- Access registers 36 and 37.
 ;;    v -- Vector registers v0-v31.
 ;;    C -- A signed 8-bit constant (-128..127)
@@ -420,6 +421,10 @@
   "@internal An integer operand with the lowest order 6 bits all ones."
   (match_operand 0 "const_int_6bitset_operand"))
 
+(define_constraint "jm8"
+  "@internal An integer operand with the lowest order 8 bits all ones."
+  (match_operand 0 "const_int_8bitset_operand"))
+
 ;;
 ;; Memory constraints follow.
 ;;
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index fefefb3..fbff24d 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -119,6 +119,12 @@
 (define_predicate "const_int_6bitset_operand"
  (and (match_code "const_int")
       (match_test "(INTVAL (op) & 63) == 63")))
+
+; An integer operand with the lowest order 8 bits all ones.
+(define_predicate "const_int_8bitset_operand"
+ (and (match_code "const_int")
+      (match_test "(INTVAL (op) & 255) == 255")))
+
 (define_predicate "nonzero_shift_count_operand"
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index ca58c42..d085fa1 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3323,7 +3323,7 @@
 
 ; Patterns for 31 bit + Esa and 64 bit + Zarch.
 
-(define_insn "*setmem_long"
+(define_insn "*setmem_long<setmem_and>"
   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
         (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y")
@@ -3336,26 +3336,10 @@
   [(set_attr "length" "8")
    (set_attr "type" "vs")])
 
-(define_insn "*setmem_long_and"
-  [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
-   (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
-        (unspec:BLK [(and:P
-		      (match_operand:P 2 "shift_count_or_setmem_operand" "Y")
-		      (match_operand:P 4 "const_int_operand"             "n"))
-		    (subreg:P (match_dup 3) <modesize>)]
-		    UNSPEC_REPLICATE_BYTE))
-   (use (match_operand:<DBL> 1 "register_operand" "d"))
-   (clobber (reg:CC CC_REGNUM))]
-  "(TARGET_64BIT || !TARGET_ZARCH) &&
-   (INTVAL (operands[4]) & 255) == 255"
-  "mvcle\t%0,%1,%Y2\;jo\t.-4"
-  [(set_attr "length" "8")
-   (set_attr "type" "vs")])
-
 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
 ; of the SImode subregs.
 
-(define_insn "*setmem_long_31z"
+(define_insn "*setmem_long_31z<setmem_and>"
   [(clobber (match_operand:TI 0 "register_operand" "=d"))
    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
         (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
@@ -3367,21 +3351,6 @@
   [(set_attr "length" "8")
    (set_attr "type" "vs")])
 
-(define_insn "*setmem_long_and_31z"
-  [(clobber (match_operand:TI 0 "register_operand" "=d"))
-   (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
-        (unspec:BLK [(and:SI
-		      (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
-		      (match_operand:SI 4 "const_int_operand"             "n"))
-		    (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
-   (use (match_operand:TI 1 "register_operand" "d"))
-   (clobber (reg:CC CC_REGNUM))]
-  "(!TARGET_64BIT && TARGET_ZARCH) &&
-   (INTVAL (operands[4]) & 255) == 255"
-  "mvcle\t%0,%1,%Y2\;jo\t.-4"
-  [(set_attr "length" "8")
-   (set_attr "type" "vs")])
-
 ;
 ; cmpmemM instruction pattern(s).
 ;
diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md
index 8a1b814..886d420 100644
--- a/gcc/config/s390/subst.md
+++ b/gcc/config/s390/subst.md
@@ -120,3 +120,28 @@
    (clobber (match_scratch:DSI 0 "=d,d"))])
 
 (define_subst_attr "cconly" "cconly_subst" "" "_cconly")
+
+
+;; setmem substitution patterns
+
+; Add an AND operation on the padding byte operand.  Only the lowest 8
+; bit are used and the rest is ignored.
+(define_subst "setmem_and_subst"
+  [(clobber (match_operand:TDI                  0 "register_operand" ""))
+   (set (mem:BLK (subreg:DSI (match_operand:TDI 1 "register_operand" "") 0))
+        (unspec:BLK [(match_operand:DSI         2 "shift_count_or_setmem_operand" "")
+		     (match_operand:DSI         3 "register_operand" "")]
+		     UNSPEC_REPLICATE_BYTE))
+   (use (match_operand:TDI                      4 "register_operand" ""))
+   (clobber (reg:CC CC_REGNUM))]
+""
+  [(clobber (match_dup 0))
+   (set (mem:BLK (subreg:DSI (match_dup 1) 0))
+	(unspec:BLK [(and:DSI (match_dup 2)
+			      (match_operand:DSI 5 "const_int_8bitset_operand" "jm8"))
+		     (match_dup 3)]
+		    UNSPEC_REPLICATE_BYTE))
+   (use (match_dup 4))
+   (clobber (reg:CC CC_REGNUM))])
+
+(define_subst_attr "setmem_and"      "setmem_and_subst" "" "_and")
-- 
1.9.1

[PATCH 3/9] S/390: Get rid of Y constraint in rotate patterns.

[Andreas Krebbel]

This patch introduces substitution patterns to add PLUS const_int, and
AND operands to patterns and uses this to rewrite the existing rotate
pattern.

gcc/ChangeLog:

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/predicates.md (const_int_6bitset_operand): New
        predicates.
	* config/s390/s390.md: Include subst.md.
	("rotl<mode>3"): New expander.
	("rotl<mode>3", "*rotl<mode>3_and"): Merge insn definitions into
	...
	("*rotl<mode>3<addr_style_op><masked_op>"): New insn definition.
	* config/s390/subst.md: New file.
---
 gcc/config/s390/constraints.md |  4 +++
 gcc/config/s390/predicates.md  |  4 +++
 gcc/config/s390/s390.c         | 23 +++++++++++-----
 gcc/config/s390/s390.md        | 31 ++++++++++-----------
 gcc/config/s390/subst.md       | 61 ++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 100 insertions(+), 23 deletions(-)
 create mode 100644 gcc/config/s390/subst.md

diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md
index c1d2c8e..60a7edf 100644
--- a/gcc/config/s390/constraints.md
+++ b/gcc/config/s390/constraints.md
@@ -36,6 +36,7 @@
 ;;         jyy: constant consisting of byte chunks being either 0 or 0xff
 ;;         jKK: constant vector with all elements having the same value and
 ;;              matching K constraint
+;;         jm6: An integer operand with the lowest order 6 bits all ones.
 ;;    t -- Access registers 36 and 37.
 ;;    v -- Vector registers v0-v31.
 ;;    C -- A signed 8-bit constant (-128..127)
@@ -415,6 +416,9 @@
 	    (match_test "const_vec_duplicate_p (op)"))
        (match_test "satisfies_constraint_K (XVECEXP (op, 0, 0))")))
 
+(define_constraint "jm6"
+  "@internal An integer operand with the lowest order 6 bits all ones."
+  (match_operand 0 "const_int_6bitset_operand"))
 
 ;;
 ;; Memory constraints follow.
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index cbc8092..fefefb3 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -115,6 +115,10 @@
   return true;
 })
 
+; An integer operand with the lowest order 6 bits all ones.
+(define_predicate "const_int_6bitset_operand"
+ (and (match_code "const_int")
+      (match_test "(INTVAL (op) & 63) == 63")))
 (define_predicate "nonzero_shift_count_operand"
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index cd53b15..43219dd 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2994,18 +2994,18 @@ s390_decompose_address (rtx addr, struct s390_address *out)
 bool
 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
 {
-  HOST_WIDE_INT off = 0;
+  rtx off = NULL_RTX;
 
   /* We can have an integer constant, an address register,
      or a sum of the two.  */
-  if (GET_CODE (op) == CONST_INT)
+  if (CONST_SCALAR_INT_P (op))
     {
-      off = INTVAL (op);
+      off = op;
       op = NULL_RTX;
     }
-  if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
+  if (op && GET_CODE (op) == PLUS && CONST_SCALAR_INT_P (XEXP (op, 1)))
     {
-      off = INTVAL (XEXP (op, 1));
+      off = XEXP (op, 1);
       op = XEXP (op, 0);
     }
   while (op && GET_CODE (op) == SUBREG)
@@ -3015,7 +3015,18 @@ s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
     return false;
 
   if (offset)
-    *offset = off;
+    {
+      if (off == NULL_RTX)
+	*offset = 0;
+      else if (CONST_INT_P (off))
+	*offset = INTVAL (off);
+      else if (CONST_WIDE_INT_P (off))
+	/* The offset will anyway be cut down to 12 bits so take just
+	   the lowest order chunk of the wide int.  */
+	*offset = CONST_WIDE_INT_ELT (off, 0);
+      else
+	gcc_unreachable ();
+    }
   if (base)
     *base = op;
 
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 65b6ce9..b7c037a 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -741,6 +741,8 @@
 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
 
+;; Subst pattern definitions
+(include "subst.md")
 
 (include "vector.md")
 
@@ -8376,28 +8378,23 @@
 ; rotl(di|si)3 instruction pattern(s).
 ;
 
-; rll, rllg
-(define_insn "rotl<mode>3"
-  [(set (match_operand:GPR 0 "register_operand" "=d")
-	(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
-		    (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+(define_expand "rotl<mode>3"
+  [(set (match_operand:GPR 0 "register_operand" "")
+        (rotate:GPR (match_operand:GPR 1 "register_operand" "")
+		    (match_operand:SI 2 "nonmemory_operand" "")))]
   "TARGET_CPU_ZARCH"
-  "rll<g>\t%0,%1,%Y2"
-  [(set_attr "op_type"  "RSE")
-   (set_attr "atype"    "reg")
-   (set_attr "z10prop" "z10_super_E1")])
+  "")
 
 ; rll, rllg
-(define_insn "*rotl<mode>3_and"
-  [(set (match_operand:GPR 0 "register_operand" "=d")
-	(rotate:GPR (match_operand:GPR 1 "register_operand" "d")
-		    (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
-			    (match_operand:SI 3 "const_int_operand"   "n"))))]
-  "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
-  "rll<g>\t%0,%1,%Y2"
+(define_insn "*rotl<mode>3<addr_style_op><masked_op>"
+  [(set (match_operand:GPR             0 "register_operand"  "=d")
+	(rotate:GPR (match_operand:GPR 1 "register_operand"   "d")
+		    (match_operand:SI  2 "nonmemory_operand" "an")))]
+  "TARGET_CPU_ZARCH"
+  "rll<g>\t%0,%1,<addr_style_op_ops>"
   [(set_attr "op_type"  "RSE")
    (set_attr "atype"    "reg")
-   (set_attr "z10prop" "z10_super_E1")])
+   (set_attr "z10prop"  "z10_super_E1")])
 
 
 ;;
diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md
new file mode 100644
index 0000000..c3761a9
--- /dev/null
+++ b/gcc/config/s390/subst.md
@@ -0,0 +1,61 @@
+;;- Machine description for GNU compiler -- S/390 / zSeries version.
+;;  Subst patterns.
+;;  Copyright (C) 2016 Free Software Foundation, Inc.
+;;  Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_code_iterator SUBST [rotate])
+
+; This expands an register/immediate operand to a register+immediate
+; operand to draw advantage of the address style operand format
+; providing a addition for free.
+(define_subst "addr_style_op_subst"
+  [(set (match_operand:DSI 0 "" "")
+        (SUBST:DSI (match_operand:DSI 1 "" "")
+		   (match_operand:SI 2 "" "")))]
+  ""
+  [(set (match_dup 0)
+        (SUBST:DSI (match_dup 1)
+		   (plus:SI (match_operand:SI 2 "register_operand" "a")
+			    (match_operand 3 "const_int_operand"   "n"))))])
+
+; Use this in the insn name.
+(define_subst_attr "addr_style_op"     "addr_style_op_subst" "" "_plus")
+
+; In the subst pattern the additional const int operand will be used
+; as displacement.  In the normal version %Y is able to print the
+; operand either as displacement or as base register.
+(define_subst_attr "addr_style_op_ops" "addr_style_op_subst" "%Y2" "%Y3(%2)")
+
+
+; This substitution adds an explicit AND operation to the second
+; operand.  This way previous operations on the now masked out bits
+; might get optimized away.
+(define_subst "masked_op_subst"
+  [(set (match_operand:DSI 0 ""           "")
+        (SUBST:DSI (match_operand:DSI 1 "" "")
+		   (match_operand:SI  2 "" "")))]
+  ""
+  [(set (match_dup 0)
+        (SUBST:DSI (match_dup 1)
+		   (and:SI (match_dup 2)
+			   (match_operand:SI 3 "const_int_6bitset_operand" "jm6"))))])
+
+; Use this in the insn name.
+(define_subst_attr "masked_op" "masked_op_subst" "" "_and")
+
-- 
1.9.1

[PATCH 9/9] S/390: Disallow SImode in s390_decompose_address

[Andreas Krebbel]

After Y is never used anymore with SImode operands we can finally
disallow SImode (if != Pmode) in s390_decompose_address.  In fact that
was the whole point of the patch series.

gcc/ChangeLog:

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.c (s390_decompose_address): Don't accept SImode
	anymore.
---
 gcc/config/s390/s390.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 43219dd..8924367 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2817,9 +2817,7 @@ s390_decompose_address (rtx addr, struct s390_address *out)
 	    return false;
 	  }
 
-      if (!REG_P (base)
-	  || (GET_MODE (base) != SImode
-	      && GET_MODE (base) != Pmode))
+      if (!REG_P (base) || GET_MODE (base) != Pmode)
 	return false;
 
       if (REGNO (base) == STACK_POINTER_REGNUM
@@ -2865,9 +2863,7 @@ s390_decompose_address (rtx addr, struct s390_address *out)
 	    return false;
 	  }
 
-      if (!REG_P (indx)
-	  || (GET_MODE (indx) != SImode
-	      && GET_MODE (indx) != Pmode))
+      if (!REG_P (indx) || GET_MODE (indx) != Pmode)
 	return false;
 
       if (REGNO (indx) == STACK_POINTER_REGNUM
-- 
1.9.1

[PATCH 2/9] S/390: Use enabled attribute overrides to disable alternatives.

[Andreas Krebbel]

So far whenever we wanted to disable an alternative we have used mode
attributes emitting constraints matching an earlier alternative
assuming that due to this the later alternative will never be chosen.

With this patch the `enabled' attribute, which so far is only set from
`cpu_facility', is overridden to 0 to disable certain alternatives.
This comes handy when defining the substitutions later and while
adding it anyway I've used it for the existing cases as well.

gcc/ChangeLog:

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.md ("op_type", "atype", "length" attributes):
	Remove RRR type.  It doesn't really exist.
	("RRer", "f0", "v0", "vf", "vd", "op1", "Rf"): Remove mode
	attributes.
	("BFP", "DFP", "nDSF", "nDFDI"): Add mode attributes.
	("*cmp<mode>_ccs", "floatdi<mode>2", "add<mode>3")
	("*add<mode>3_cc", "*add<mode>3_cconly", "sub<mode>3")
	("*sub<mode>3_cc", "*sub<mode>3_cconly", "mul<mode>3")
	("fma<mode>4", "fms<mode>4", "div<mode>3", "*neg<mode>2")
	("*abs<mode>2", "*negabs<mode>2", "sqrt<mode>2"): Override
	`enabled' attribute.
---
 gcc/config/s390/s390.md | 215 +++++++++++++++++++++++++-----------------------
 1 file changed, 111 insertions(+), 104 deletions(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 8f92018..65b6ce9 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -366,7 +366,7 @@
 ;; Used to determine defaults for length and other attribute values.
 
 (define_attr "op_type"
-  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
+  "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
   (const_string "NN"))
 
 ;; Instruction type attribute used for scheduling.
@@ -393,7 +393,7 @@
 ;;   reg: Instruction does not use the agen unit
 
 (define_attr "atype" "agen,reg"
-  (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
+  (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
 		(const_string "reg")
 		(const_string "agen")))
 
@@ -434,8 +434,8 @@
 ;; Length in bytes.
 
 (define_attr "length" ""
-  (cond [(eq_attr "op_type" "E,RR")		              (const_int 2)
-         (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR")  (const_int 4)]
+  (cond [(eq_attr "op_type" "E,RR")		          (const_int 2)
+         (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF")  (const_int 4)]
     (const_int 6)))
 
 
@@ -618,27 +618,14 @@
 ;; fp register operands.  The following attributes allow to merge the bfp and
 ;; dfp variants in a single insn definition.
 
-;; This attribute is used to set op_type accordingly.
-(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
-                        (DD "RRR") (SD "RRR")])
-
-;; This attribute is used in the operand constraint list in order to have the
-;; first and the second operand match for bfp modes.
-(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
-
-;; This attribute is used to merge the scalar vector instructions into
-;; the FP patterns.  For non-supported modes (all but DF) it expands
-;; to constraints which are supposed to be matched by an earlier
-;; variant.
-(define_mode_attr v0      [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")])
-(define_mode_attr vf      [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")])
-(define_mode_attr vd      [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")])
-
-;; This attribute is used in the operand list of the instruction to have an
-;; additional operand for the dfp instructions.
-(define_mode_attr op1 [(TF "") (DF "") (SF "")
-                       (TD "%1,") (DD "%1,") (SD "%1,")])
-
+;; These mode attributes are supposed to be used in the `enabled' insn
+;; attribute to disable certain alternatives for certain modes.
+(define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
+(define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
+(define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
+(define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
+			(TD "0") (DD "0") (DD "0")
+			(TI "0") (DI "*") (SI "0")])
 
 ;; This attribute is used in the operand constraint list
 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
@@ -648,10 +635,6 @@
 ;; target operand uses the same fp register.
 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
 
-;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
-;; This is used to disable the memory alternative in TFmode patterns.
-(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
-
 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
 ;; within instruction mnemonics.
 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
@@ -1260,13 +1243,14 @@
 (define_insn "*cmp<mode>_ccs"
   [(set (reg CC_REGNUM)
         (compare (match_operand:FP 0 "register_operand" "f,f")
-                 (match_operand:FP 1 "general_operand"  "f,<Rf>")))]
+                 (match_operand:FP 1 "general_operand"  "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
    c<xde><bt>r\t%0,%1
    c<xde>b\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
-    (set_attr "type"  "fsimp<mode>")])
+    (set_attr "type"  "fsimp<mode>")
+    (set_attr "enabled" "*,<DSF>")])
 
 ; wfcedbs, wfchdbs, wfchedbs
 (define_insn "*vec_cmp<insn_cmp>df_cconly"
@@ -4731,15 +4715,16 @@
 
 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
 (define_insn "floatdi<mode>2"
-  [(set (match_operand:FP           0 "register_operand" "=f,<vf>")
-        (float:FP (match_operand:DI 1 "register_operand"  "d,<vd>")))]
+  [(set (match_operand:FP           0 "register_operand" "=f,v")
+        (float:FP (match_operand:DI 1 "register_operand"  "d,v")))]
   "TARGET_ZARCH && TARGET_HARD_FLOAT"
   "@
    c<xde>g<bt>r\t%0,%1
    wcdgb\t%v0,%v1,0,0"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "type"         "itof<mode>" )
-   (set_attr "cpu_facility" "*,vec")])
+   (set_attr "cpu_facility" "*,vec")
+   (set_attr "enabled"      "*,<DFDI>")])
 
 ; cxfbr, cdfbr, cefbr
 (define_insn "floatsi<mode>2"
@@ -5498,47 +5483,53 @@
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 ; FIXME: wfadb does not clobber cc
 (define_insn "add<mode>3"
-  [(set (match_operand:FP 0 "register_operand"                 "=f,   f,<vf>")
-        (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
-		 (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))
+  [(set (match_operand:FP 0 "register_operand"              "=f,f,f,v")
+        (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
+		 (match_operand:FP 2 "general_operand"       "f,f,R,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
-   a<xde><bt>r\t%0,<op1>%2
+   a<xde>tr\t%0,%1,%2
+   a<xde>br\t%0,%2
    a<xde>b\t%0,%2
    wfadb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fsimp<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 (define_insn "*add<mode>3_cc"
   [(set (reg CC_REGNUM)
-	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
-			  (match_operand:FP 2 "general_operand"      " f,<Rf>"))
+	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+			  (match_operand:FP 2 "general_operand"       "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (set (match_operand:FP 0 "register_operand" "=f,f")
+   (set (match_operand:FP 0 "register_operand" "=f,f,f")
 	(plus:FP (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   a<xde><bt>r\t%0,<op1>%2
+   a<xde>tr\t%0,%1,%2
+   a<xde>br\t%0,%2
    a<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
 
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
 (define_insn "*add<mode>3_cconly"
   [(set (reg CC_REGNUM)
-	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
-			   (match_operand:FP 2 "general_operand"      " f,<Rf>"))
+	(compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+			  (match_operand:FP 2 "general_operand"       "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (clobber (match_scratch:FP 0 "=f,f"))]
+   (clobber (match_scratch:FP 0 "=f,f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   a<xde><bt>r\t%0,<op1>%2
+   a<xde>tr\t%0,%1,%2
+   a<xde>br\t%0,%2
    a<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
 
 ;
 ; Pointer add instruction patterns
@@ -5922,47 +5913,53 @@
 
 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "sub<mode>3"
-  [(set (match_operand:FP           0 "register_operand"   "=f,   f,<vf>")
-        (minus:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
-                  (match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))
+  [(set (match_operand:FP           0 "register_operand" "=f,f,f,v")
+        (minus:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
+                  (match_operand:FP 2 "general_operand"   "f,f,R,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
-   s<xde><bt>r\t%0,<op1>%2
+   s<xde>tr\t%0,%1,%2
+   s<xde>br\t%0,%2
    s<xde>b\t%0,%2
    wfsdb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fsimp<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "*sub<mode>3_cc"
   [(set (reg CC_REGNUM)
-	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
-                           (match_operand:FP 2 "general_operand"      "f,<Rf>"))
+	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+                           (match_operand:FP 2 "general_operand"      "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (set (match_operand:FP 0 "register_operand" "=f,f")
+   (set (match_operand:FP 0 "register_operand" "=f,f,f")
 	(minus:FP (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   s<xde><bt>r\t%0,<op1>%2
+   s<xde>tr\t%0,%1,%2
+   s<xde>br\t%0,%2
    s<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
 
 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
 (define_insn "*sub<mode>3_cconly"
   [(set (reg CC_REGNUM)
-	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
-			   (match_operand:FP 2 "general_operand"      "f,<Rf>"))
+	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+			   (match_operand:FP 2 "general_operand"      "f,f,R"))
 		 (match_operand:FP 3 "const0_operand" "")))
-   (clobber (match_scratch:FP 0 "=f,f"))]
+   (clobber (match_scratch:FP 0 "=f,f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
-   s<xde><bt>r\t%0,<op1>%2
+   s<xde>tr\t%0,%1,%2
+   s<xde>br\t%0,%2
    s<xde>b\t%0,%2"
-  [(set_attr "op_type"  "<RRer>,RXE")
-   (set_attr "type"     "fsimp<mode>")])
+  [(set_attr "op_type"  "RRF,RRE,RXE")
+   (set_attr "type"     "fsimp<mode>")
+   (set_attr "enabled"  "<nBFP>,<nDFP>,<DSF>")])
 
 
 ;;
@@ -6344,24 +6341,26 @@
 
 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
 (define_insn "mul<mode>3"
-  [(set (match_operand:FP          0 "register_operand"        "=f,   f,<vf>")
-        (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,   0,<v0>")
-                 (match_operand:FP 2 "general_operand"          "f,<Rf>,<vf>")))]
+  [(set (match_operand:FP          0 "register_operand"     "=f,f,f,v")
+        (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
+                 (match_operand:FP 2 "general_operand"       "f,f,R,v")))]
   "TARGET_HARD_FLOAT"
   "@
-   m<xdee><bt>r\t%0,<op1>%2
+   m<xdee>tr\t%0,%1,%2
+   m<xdee>br\t%0,%2
    m<xdee>b\t%0,%2
    wfmdb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fmul<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 ; madbr, maebr, maxb, madb, maeb
 (define_insn "fma<mode>4"
-  [(set (match_operand:DSF          0 "register_operand"     "=f,f,<vf>")
-	(fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
-		 (match_operand:DSF 2 "nonimmediate_operand"  "f,R,<vf>")
-		 (match_operand:DSF 3 "register_operand"      "0,0,<v0>")))]
+  [(set (match_operand:DSF          0 "register_operand"     "=f,f,v")
+	(fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
+		 (match_operand:DSF 2 "nonimmediate_operand"  "f,R,v")
+		 (match_operand:DSF 3 "register_operand"      "0,0,v")))]
   "TARGET_HARD_FLOAT"
   "@
    ma<xde>br\t%0,%1,%2
@@ -6369,14 +6368,15 @@
    wfmadb\t%v0,%v1,%v2,%v3"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fmadd<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "enabled"      "*,*,<DFDI>")])
 
 ; msxbr, msdbr, msebr, msxb, msdb, mseb
 (define_insn "fms<mode>4"
-  [(set (match_operand:DSF                   0 "register_operand"     "=f,f,<vf>")
-	(fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,<vf>")
-		 (match_operand:DSF          2 "nonimmediate_operand"  "f,R,<vf>")
-		 (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,<v0>"))))]
+  [(set (match_operand:DSF                   0 "register_operand"     "=f,f,v")
+	(fma:DSF (match_operand:DSF          1 "nonimmediate_operand" "%f,f,v")
+		 (match_operand:DSF          2 "nonimmediate_operand"  "f,R,v")
+		 (neg:DSF (match_operand:DSF 3 "register_operand"      "0,0,v"))))]
   "TARGET_HARD_FLOAT"
   "@
    ms<xde>br\t%0,%1,%2
@@ -6384,7 +6384,8 @@
    wfmsdb\t%v0,%v1,%v2,%v3"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fmadd<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "enabled"      "*,*,<DFDI>")])
 
 ;;
 ;;- Divide and modulo instructions.
@@ -6810,17 +6811,19 @@
 
 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
 (define_insn "div<mode>3"
-  [(set (match_operand:FP         0 "register_operand"   "=f,   f,<vf>")
-        (div:FP (match_operand:FP 1 "register_operand" "<f0>,   0,<v0>")
-		(match_operand:FP 2 "general_operand"     "f,<Rf>,<vf>")))]
+  [(set (match_operand:FP         0 "register_operand" "=f,f,f,v")
+        (div:FP (match_operand:FP 1 "register_operand"  "f,0,0,v")
+		(match_operand:FP 2 "general_operand"   "f,f,R,v")))]
   "TARGET_HARD_FLOAT"
   "@
-   d<xde><bt>r\t%0,<op1>%2
+   d<xde>tr\t%0,%1,%2
+   d<xde>br\t%0,%2
    d<xde>b\t%0,%2
    wfddb\t%v0,%v1,%v2"
-  [(set_attr "op_type"      "<RRer>,RXE,VRR")
+  [(set_attr "op_type"      "RRF,RRE,RXE,VRR")
    (set_attr "type"         "fdiv<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,*,vec")
+   (set_attr "enabled"      "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
 
 
 ;;
@@ -8031,8 +8034,8 @@
 ; lcxbr, lcdbr, lcebr
 ; FIXME: wflcdb does not clobber cc
 (define_insn "*neg<mode>2"
-  [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
-        (neg:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
+  [(set (match_operand:BFP          0 "register_operand" "=f,v")
+        (neg:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
@@ -8040,7 +8043,8 @@
    wflcdb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "cpu_facility" "*,vec")
-   (set_attr "type"         "fsimp<mode>,*")])
+   (set_attr "type"         "fsimp<mode>,*")
+   (set_attr "enabled"      "*,<DFDI>")])
 
 
 ;;
@@ -8153,8 +8157,8 @@
 ; lpxbr, lpdbr, lpebr
 ; FIXME: wflpdb does not clobber cc
 (define_insn "*abs<mode>2"
-  [(set (match_operand:BFP          0 "register_operand" "=f,<vf>")
-        (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>")))
+  [(set (match_operand:BFP          0 "register_operand" "=f,v")
+        (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
@@ -8162,7 +8166,8 @@
     wflpdb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "cpu_facility" "*,vec")
-   (set_attr "type"         "fsimp<mode>,*")])
+   (set_attr "type"         "fsimp<mode>,*")
+   (set_attr "enabled"      "*,<DFDI>")])
 
 
 ;;
@@ -8268,8 +8273,8 @@
 ; lnxbr, lndbr, lnebr
 ; FIXME: wflndb does not clobber cc
 (define_insn "*negabs<mode>2"
-  [(set (match_operand:BFP                   0 "register_operand" "=f,<vf>")
-        (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,<vf>"))))
+  [(set (match_operand:BFP                   0 "register_operand" "=f,v")
+        (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand"  "f,v"))))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT"
   "@
@@ -8277,7 +8282,8 @@
    wflndb\t%0,%1"
   [(set_attr "op_type"      "RRE,VRR")
    (set_attr "cpu_facility" "*,vec")
-   (set_attr "type"         "fsimp<mode>,*")])
+   (set_attr "type"         "fsimp<mode>,*")
+   (set_attr "enabled"      "*,<DFDI>")])
 
 ;;
 ;;- Square root instructions.
@@ -8289,8 +8295,8 @@
 
 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
 (define_insn "sqrt<mode>2"
-  [(set (match_operand:BFP           0 "register_operand" "=f,   f,<vf>")
-	(sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,<Rf>,<vf>")))]
+  [(set (match_operand:BFP           0 "register_operand" "=f,f,v")
+	(sqrt:BFP (match_operand:BFP 1 "general_operand"   "f,R,v")))]
   "TARGET_HARD_FLOAT"
   "@
    sq<xde>br\t%0,%1
@@ -8298,7 +8304,8 @@
    wfsqdb\t%v0,%v1"
   [(set_attr "op_type"      "RRE,RXE,VRR")
    (set_attr "type"         "fsqrt<mode>")
-   (set_attr "cpu_facility" "*,*,vec")])
+   (set_attr "cpu_facility" "*,*,vec")
+   (set_attr "enabled"      "*,<DSF>,<DFDI>")])
 
 
 ;;
-- 
1.9.1

[PATCH 4/9] S/390: Get rid of Y constraint in left and logical right shift patterns.

[Andreas Krebbel]

With this patch the substitution patterns added earlier are used for
the logical right shift and all the left shift patterns.

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.md ("<shift><mode>3"): Change predicate of
	op2 to nonmemory_operand.
	("*<shift>di3_31", "*<shift>di3_31_and"):
	Merge into single pattern definition ...
	("*<shift>di3_31<addr_style_op><masked_op>"): New pattern.
	("*<shift><mode>3", "*<shift><mode>3_and"): Merge into single
	pattern definition ...
	("*<shift><mode>3<addr_style_op><masked_op>"): New pattern.
	* config/s390/subst.md: Add ashift and lshiftrt to SUBST
	iterator.
---
 gcc/config/s390/s390.md  | 55 ++++++++++++++----------------------------------
 gcc/config/s390/subst.md |  2 +-
 2 files changed, 17 insertions(+), 40 deletions(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index b7c037a..771d1e9 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -8408,60 +8408,37 @@
 (define_expand "<shift><mode>3"
   [(set (match_operand:DSI 0 "register_operand" "")
         (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
-                   (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
+                   (match_operand:SI 2 "nonmemory_operand" "")))]
   ""
   "")
 
+; ESA 64 bit register pair shift with reg or imm shift count
 ; sldl, srdl
-(define_insn "*<shift>di3_31"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-        (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
-                  (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+(define_insn "*<shift>di3_31<addr_style_op><masked_op>"
+  [(set (match_operand:DI 0 "register_operand"            "=d")
+        (SHIFT:DI (match_operand:DI 1 "register_operand"   "0")
+                  (match_operand:SI 2 "nonmemory_operand" "an")))]
   "!TARGET_ZARCH"
-  "s<lr>dl\t%0,%Y2"
+  "s<lr>dl\t%0,<addr_style_op_ops>"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")
    (set_attr "z196prop" "z196_cracked")])
 
-; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3"
-  [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
-        (SHIFT:GPR (match_operand:GPR 1 "register_operand"             "<d0>,d")
-                   (match_operand:SI 2 "shift_count_or_setmem_operand"    "Y,Y")))]
-  ""
-  "@
-   s<lr>l<g>\t%0,<1>%Y2
-   s<lr>l<gk>\t%0,%1,%Y2"
-  [(set_attr "op_type"  "RS<E>,RSY")
-   (set_attr "atype"    "reg,reg")
-   (set_attr "cpu_facility" "*,z196")
-   (set_attr "z10prop" "z10_super_E1,*")])
-
-; sldl, srdl
-(define_insn "*<shift>di3_31_and"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-        (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
-                  (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
-			  (match_operand:SI 3 "const_int_operand"   "n"))))]
-  "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
-  "s<lr>dl\t%0,%Y2"
-  [(set_attr "op_type"  "RS")
-   (set_attr "atype"    "reg")])
 
+; 64 bit register shift with reg or imm shift count
 ; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3_and"
-  [(set (match_operand:GPR 0 "register_operand"                                 "=d,d")
-        (SHIFT:GPR (match_operand:GPR 1 "register_operand"                    "<d0>,d")
-                   (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand"   "Y,Y")
-			   (match_operand:SI 3 "const_int_operand"               "n,n"))))]
-  "(INTVAL (operands[3]) & 63) == 63"
+(define_insn "*<shift><mode>3<addr_style_op><masked_op>"
+  [(set (match_operand:GPR 0 "register_operand"              "=d, d")
+        (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
+                   (match_operand:SI 2 "nonmemory_operand"   "an,an")))]
+  ""
   "@
-   s<lr>l<g>\t%0,<1>%Y2
-   s<lr>l<gk>\t%0,%1,%Y2"
+   s<lr>l<g>\t%0,<1><addr_style_op_ops>
+   s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
   [(set_attr "op_type"  "RS<E>,RSY")
    (set_attr "atype"    "reg,reg")
    (set_attr "cpu_facility" "*,z196")
-   (set_attr "z10prop" "z10_super_E1,*")])
+   (set_attr "z10prop"  "z10_super_E1,*")])
 
 ;
 ; ashr(di|si)3 instruction pattern(s).
diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md
index c3761a9..907676a 100644
--- a/gcc/config/s390/subst.md
+++ b/gcc/config/s390/subst.md
@@ -19,7 +19,7 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_code_iterator SUBST [rotate])
+(define_code_iterator SUBST [rotate ashift lshiftrt])
 
 ; This expands an register/immediate operand to a register+immediate
 ; operand to draw advantage of the address style operand format
-- 
1.9.1

[PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[Andreas Krebbel]

When processing substitutions the operands are renumbered.  To find a
free operand number the array used_operands_numbers is used.
Currently this array is used to assign new numbers before all the
RTXes in the vector have been processed.  I did run into problems with
this for insns where a match_dup occurred in a later (use ...) operand
referring to an earlier operand (e.g. s390.md "setmem_long").

The patch splits the loop doing the processing into two in order to
have all the operand numbers collected already when assigning new
numbers.

Bootstrapped and regtested on s390, s390x, and x86_64.

Ok for mainline?

Bye,

-Andreas-

gcc/ChangeLog:

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gensupport.c (process_substs_on_one_elem): Split loop to
	complete mark_operands_used_in_match_dup on all expressions in the
	vector first.
	(adjust_operands_numbers): Inline into process_substs_on_one_elem
	and remove function.
---
 gcc/gensupport.c | 45 ++++++++++++++++++++-------------------------
 1 file changed, 20 insertions(+), 25 deletions(-)

diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index 8c5a1ab..de29579 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -126,7 +126,10 @@ static const char * duplicate_each_alternative (const char * str, int n_dup);
 
 typedef const char * (*constraints_handler_t) (const char *, int);
 static rtx alter_constraints (rtx, int, constraints_handler_t);
-static rtx adjust_operands_numbers (rtx);
+
+static void mark_operands_used_in_match_dup (rtx);
+static void renumerate_operands_in_pattern (rtx);
+
 static rtx replace_duplicating_operands_in_pattern (rtx);
 \f
 /* Make a version of gen_rtx_CONST_INT so that GEN_INT can be used in
@@ -1844,7 +1847,18 @@ process_substs_on_one_elem (struct queue_elem *elem,
 	  subst_pattern = alter_constraints (subst_pattern, alternatives,
 					     duplicate_each_alternative);
 
-	  subst_pattern = adjust_operands_numbers (subst_pattern);
+	  mark_operands_used_in_match_dup (subst_pattern);
+	  RTVEC_ELT (subst_pattern_vec, j) = subst_pattern;
+	}
+
+      for (j = 0; j < XVECLEN (subst_elem->data, 3); j++)
+	{
+	  subst_pattern = RTVEC_ELT (subst_pattern_vec, j);
+
+	  /* The number of MATCH_OPERANDs in the output pattern might
+	     change.  This routine assigns new numbers to the
+	     MATCH_OPERAND expressions to avoid collisions.  */
+	  renumerate_operands_in_pattern (subst_pattern);
 
 	  /* Substitute match_dup and match_op_dup in the new pattern and
 	     duplicate constraints.  */
@@ -1857,7 +1871,6 @@ process_substs_on_one_elem (struct queue_elem *elem,
 	  if (GET_CODE (elem->data) == DEFINE_EXPAND)
 	    remove_constraints (subst_pattern);
 
-	  RTVEC_ELT (subst_pattern_vec, j) = subst_pattern;
 	}
       XVEC (elem->data, 1) = subst_pattern_vec;
 
@@ -1927,7 +1940,7 @@ mark_operands_from_match_dup (rtx pattern)
     }
 }
 
-/* This is a subroutine of adjust_operands_numbers.
+/* This is a subroutine of process_substs_on_one_elem.
    It goes through all expressions in PATTERN and when MATCH_DUP is
    met, all MATCH_OPERANDs inside it is marked as occupied.  The
    process of marking is done by routin mark_operands_from_match_dup.  */
@@ -1973,10 +1986,9 @@ find_first_unused_number_of_operand ()
   return MAX_OPERANDS;
 }
 
-/* This is subroutine of adjust_operands_numbers.
-   It visits all expressions in PATTERN and assigns not-occupied
-   operand indexes to MATCH_OPERANDs and MATCH_OPERATORs of this
-   PATTERN.  */
+/* This is a subroutine of process_substs_on_one_elem.  It visits all
+   expressions in PATTERN and assigns not-occupied operand indexes to
+   MATCH_OPERANDs and MATCH_OPERATORs of this PATTERN.  */
 static void
 renumerate_operands_in_pattern (rtx pattern)
 {
@@ -2011,23 +2023,6 @@ renumerate_operands_in_pattern (rtx pattern)
     }
 }
 
-/* If output pattern of define_subst contains MATCH_DUP, then this
-   expression would be replaced with the pattern, matched with
-   MATCH_OPERAND from input pattern.  This pattern could contain any
-   number of MATCH_OPERANDs, MATCH_OPERATORs etc., so it's possible
-   that a MATCH_OPERAND from output_pattern (if any) would have the
-   same number, as MATCH_OPERAND from copied pattern.  To avoid such
-   indexes overlapping, we assign new indexes to MATCH_OPERANDs,
-   laying in the output pattern outside of MATCH_DUPs.  */
-static rtx
-adjust_operands_numbers (rtx pattern)
-{
-  mark_operands_used_in_match_dup (pattern);
-
-  renumerate_operands_in_pattern (pattern);
-
-  return pattern;
-}
 
 /* Generate RTL expression
    (match_dup OPNO)
-- 
1.9.1

[PATCH 7/9] S/390: Get rid of Y constraint in vector.md.

[Andreas Krebbel]

This finally removes the Y constraint from the vector patterns while
folding some of them using a code iterator.

gcc/ChangeLog:

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/subst.md (DSI_VI): New mode iterator.
	("addr_style_op_subst"): Use DSI_VI instead of DSI.
	* config/s390/vector.md ("vec_set<mode>"): Move expander before
	the insn definition.
	("*vec_set<mode>"): Change predicate and add alternative to
	support only either register or const_int operands as element
	selector.
	("*vec_set<mode>_plus"): New pattern to support reg + const_int
	operands.
	("vec_extract<mode>"): New expander.
	("*vec_extract<mode>"): New insn definition supporting reg and
	const_int element selectors.
	("*vec_extract<mode>_plus"): New insn definition supporting
	reg+const_int element selectors.
	("rotl<mode>3", "ashl<mode>3", "ashr<mode>3"): Merge into the
	following expander+insn definition.
	("<vec_shifts_name><mode>3"): New expander.
	("*<vec_shifts_name><mode>3<addr_style_op>"): New insn definition.
---
 gcc/config/s390/subst.md  |  13 ++---
 gcc/config/s390/vector.md | 127 +++++++++++++++++++++++++++-------------------
 2 files changed, 81 insertions(+), 59 deletions(-)

diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md
index 3becf20..8a1b814 100644
--- a/gcc/config/s390/subst.md
+++ b/gcc/config/s390/subst.md
@@ -20,19 +20,20 @@
 ;; <http://www.gnu.org/licenses/>.
 
 (define_code_iterator SUBST [rotate ashift lshiftrt ashiftrt])
+(define_mode_iterator DSI_VI [SI DI V2QI V4QI V8QI V16QI V2HI V4HI V8HI V2SI V4SI V2DI])
 
 ; This expands an register/immediate operand to a register+immediate
 ; operand to draw advantage of the address style operand format
 ; providing a addition for free.
 (define_subst "addr_style_op_subst"
-  [(set (match_operand:DSI 0 "" "")
-        (SUBST:DSI (match_operand:DSI 1 "" "")
-		   (match_operand:SI 2 "" "")))]
+  [(set (match_operand:DSI_VI 0 "" "")
+        (SUBST:DSI_VI (match_operand:DSI_VI 1 "" "")
+		      (match_operand:SI 2 "" "")))]
   ""
   [(set (match_dup 0)
-        (SUBST:DSI (match_dup 1)
-		   (plus:SI (match_operand:SI 2 "register_operand" "a")
-			    (match_operand 3 "const_int_operand"   "n"))))])
+        (SUBST:DSI_VI (match_dup 1)
+		      (plus:SI (match_operand:SI 2 "register_operand" "a")
+			       (match_operand 3 "const_int_operand"   "n"))))])
 
 ; Use this in the insn name.
 (define_subst_attr "addr_style_op"     "addr_style_op_subst" "" "_plus")
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index cc3287c..2b8e9bf 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -307,47 +307,82 @@
 
 ; vec_store_lanes?
 
+; vec_set is supposed to *modify* an existing vector so operand 0 is
+; duplicated as input operand.
+(define_expand "vec_set<mode>"
+  [(set (match_operand:V                    0 "register_operand"              "")
+	(unspec:V [(match_operand:<non_vec> 1 "general_operand"               "")
+		   (match_operand:SI        2 "shift_count_or_setmem_operand" "")
+		   (match_dup 0)]
+		   UNSPEC_VEC_SET))]
+  "TARGET_VX")
+
 ; FIXME: Support also vector mode operands for 1
 ; FIXME: A target memory operand seems to be useful otherwise we end
 ; up with vl vlvgg vst.  Shouldn't the middle-end be able to handle
 ; that itself?
 (define_insn "*vec_set<mode>"
-  [(set (match_operand:V                    0 "register_operand"             "=v, v,v")
-	(unspec:V [(match_operand:<non_vec> 1 "general_operand"               "d,QR,K")
-		   (match_operand:SI        2 "shift_count_or_setmem_operand" "Y, I,I")
-		   (match_operand:V         3 "register_operand"              "0, 0,0")]
+  [(set (match_operand:V                    0 "register_operand"  "=v, v,v")
+	(unspec:V [(match_operand:<non_vec> 1 "general_operand"    "d,QR,K")
+		   (match_operand:SI        2 "nonmemory_operand" "an, I,I")
+		   (match_operand:V         3 "register_operand"   "0, 0,0")]
 		  UNSPEC_VEC_SET))]
-  "TARGET_VX"
+  "TARGET_VX
+   && (!CONST_INT_P (operands[2])
+       || UINTVAL (operands[2]) < GET_MODE_NUNITS (<V:MODE>mode))"
   "@
    vlvg<bhfgq>\t%v0,%1,%Y2
    vle<bhfgq>\t%v0,%1,%2
    vlei<bhfgq>\t%v0,%1,%2"
   [(set_attr "op_type" "VRS,VRX,VRI")])
 
-; vec_set is supposed to *modify* an existing vector so operand 0 is
-; duplicated as input operand.
-(define_expand "vec_set<mode>"
-  [(set (match_operand:V                    0 "register_operand"              "")
-	(unspec:V [(match_operand:<non_vec> 1 "general_operand"               "")
-		   (match_operand:SI        2 "shift_count_or_setmem_operand" "")
-		   (match_dup 0)]
-		   UNSPEC_VEC_SET))]
-  "TARGET_VX")
+(define_insn "*vec_set<mode>_plus"
+  [(set (match_operand:V                      0 "register_operand" "=v")
+	(unspec:V [(match_operand:<non_vec>   1 "general_operand"   "d")
+		   (plus:SI (match_operand:SI 2 "register_operand"  "a")
+			    (match_operand:SI 4 "const_int_operand" "n"))
+		   (match_operand:V           3 "register_operand"  "0")]
+		  UNSPEC_VEC_SET))]
+  "TARGET_VX"
+  "vlvg<bhfgq>\t%v0,%1,%4(%2)"
+  [(set_attr "op_type" "VRS")])
+
 
 ; FIXME: Support also vector mode operands for 0
 ; FIXME: This should be (vec_select ..) or something but it does only allow constant selectors :(
 ; This is used via RTL standard name as well as for expanding the builtin
-(define_insn "vec_extract<mode>"
-  [(set (match_operand:<non_vec> 0 "nonimmediate_operand"                        "=d,QR")
-	(unspec:<non_vec> [(match_operand:V  1 "register_operand"                " v, v")
-			   (match_operand:SI 2 "shift_count_or_setmem_operand"   " Y, I")]
+(define_expand "vec_extract<mode>"
+  [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "")
+	(unspec:<non_vec> [(match_operand:V  1 "register_operand" "")
+			   (match_operand:SI 2 "shift_count_or_setmem_operand" "")]
 			  UNSPEC_VEC_EXTRACT))]
-  "TARGET_VX"
+  "TARGET_VX")
+
+(define_insn "*vec_extract<mode>"
+  [(set (match_operand:<non_vec> 0 "nonimmediate_operand"          "=d,QR")
+	(unspec:<non_vec> [(match_operand:V  1 "register_operand"   "v, v")
+			   (match_operand:SI 2 "nonmemory_operand" "an, I")]
+			  UNSPEC_VEC_EXTRACT))]
+  "TARGET_VX
+   && (!CONST_INT_P (operands[2])
+       || UINTVAL (operands[2]) < GET_MODE_NUNITS (<V:MODE>mode))"
   "@
    vlgv<bhfgq>\t%0,%v1,%Y2
    vste<bhfgq>\t%v1,%0,%2"
   [(set_attr "op_type" "VRS,VRX")])
 
+(define_insn "*vec_extract<mode>_plus"
+  [(set (match_operand:<non_vec>                      0 "nonimmediate_operand" "=d,QR")
+	(unspec:<non_vec> [(match_operand:V           1 "register_operand"      "v, v")
+			   (plus:SI (match_operand:SI 2 "nonmemory_operand"     "a, I")
+				    (match_operand:SI 3 "const_int_operand"     "n, I"))]
+			   UNSPEC_VEC_EXTRACT))]
+  "TARGET_VX"
+  "@
+   vlgv<bhfgq>\t%0,%v1,%3(%2)
+   vste<bhfgq>\t%v1,%0,%2"
+  [(set_attr "op_type" "VRS,VRX")])
+
 (define_expand "vec_init<V_HW:mode>"
   [(match_operand:V_HW 0 "register_operand" "")
    (match_operand:V_HW 1 "nonmemory_operand" "")]
@@ -667,17 +702,6 @@
   [(set_attr "op_type" "VRR")])
 
 
-; Vector rotate instructions
-
-; Each vector element rotated by a scalar
-; verllb, verllh, verllf, verllg
-(define_insn "rotl<mode>3"
-  [(set (match_operand:VI            0 "register_operand"             "=v")
-	(rotate:VI (match_operand:VI 1 "register_operand"              "v")
-		   (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
-  "TARGET_VX"
-  "verll<bhfgq>\t%v0,%v1,%Y2"
-  [(set_attr "op_type" "VRS")])
 
 ; Each vector element rotated by the corresponding vector element
 ; verllvb, verllvh, verllvf, verllvg
@@ -690,36 +714,33 @@
   [(set_attr "op_type" "VRR")])
 
 
-; Shift each element by scalar value
+; Vector rotate and shift by scalar instructions
 
-; veslb, veslh, veslf, veslg
-(define_insn "ashl<mode>3"
-  [(set (match_operand:VI            0 "register_operand"             "=v")
-	(ashift:VI (match_operand:VI 1 "register_operand"              "v")
-		   (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
-  "TARGET_VX"
-  "vesl<bhfgq>\t%v0,%v1,%Y2"
-  [(set_attr "op_type" "VRS")])
+(define_code_iterator VEC_SHIFTS [ashift ashiftrt lshiftrt rotate])
+(define_code_attr vec_shifts_name [(ashift "ashl")    (ashiftrt "ashr")
+				   (lshiftrt "lshr")  (rotate "rotl")])
+(define_code_attr vec_shifts_mnem [(ashift "vesl")    (ashiftrt "vesra")
+				   (lshiftrt "vesrl") (rotate "verll")])
 
-; vesrab, vesrah, vesraf, vesrag
-(define_insn "ashr<mode>3"
-  [(set (match_operand:VI              0 "register_operand"             "=v")
-	(ashiftrt:VI (match_operand:VI 1 "register_operand"              "v")
-		     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
-  "TARGET_VX"
-  "vesra<bhfgq>\t%v0,%v1,%Y2"
-  [(set_attr "op_type" "VRS")])
+; Each vector element rotated by a scalar
+(define_expand "<vec_shifts_name><mode>3"
+  [(set (match_operand:VI 0 "register_operand" "")
+	(VEC_SHIFTS:VI (match_operand:VI 1 "register_operand" "")
+		       (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
+  "TARGET_VX")
 
+; verllb, verllh, verllf, verllg
+; veslb,  veslh,  veslf,  veslg
+; vesrab, vesrah, vesraf, vesrag
 ; vesrlb, vesrlh, vesrlf, vesrlg
-(define_insn "lshr<mode>3"
-  [(set (match_operand:VI              0 "register_operand"             "=v")
-	(lshiftrt:VI (match_operand:VI 1 "register_operand"              "v")
-		     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+(define_insn "*<vec_shifts_name><mode>3<addr_style_op>"
+  [(set (match_operand:VI                0 "register_operand"  "=v")
+	(VEC_SHIFTS:VI (match_operand:VI 1 "register_operand"   "v")
+		       (match_operand:SI 2 "nonmemory_operand" "an")))]
   "TARGET_VX"
-  "vesrl<bhfgq>\t%v0,%v1,%Y2"
+  "<vec_shifts_mnem><bhfgq>\t%v0,%v1,%Y2"
   [(set_attr "op_type" "VRS")])
 
-
 ; Shift each element by corresponding vector element
 
 ; veslvb, veslvh, veslvf, veslvg
-- 
1.9.1

[PATCH 5/9] S/390: Get rid of Y constraint in arithmetic right shift patterns.

[Andreas Krebbel]

The arithmetic shift patterns set also the condition code.  This adds
more substitution potential.  Depending on whether the actual result
or the CC output will be used 3 different variants of each of these
patterns are needed.  This multiplied with the PLUS and the AND
operands from the earlier substitutions enables a lot of folding.

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.md ("*ashrdi3_cc_31")
	("*ashrdi3_cconly_31""*ashrdi3_cc_31_and")
	("*ashrdi3_cconly_31_and", "*ashrdi3_31_and", "*ashrdi3_31"):
	Merge insn definitions into ...
	("*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"):
	New pattern definition.
	("*ashr<mode>3_cc", "*ashr<mode>3_cconly", "ashr<mode>3", )
	("*ashr<mode>3_cc_and", "*ashr<mode>3_cconly_and")
	("*ashr<mode>3_and"): Merge insn definitions into ...
	("*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"):
	New pattern definition.
	* config/s390/subst.md ("addr_style_op_cc_subst")
	("masked_op_cc_subst", "setcc_subst", "cconly_subst"): New
	substitutions patterns plus attributes.
	Add ashiftrt to SUBST iterator.
---
 gcc/config/s390/s390.md  | 181 ++++++-----------------------------------------
 gcc/config/s390/subst.md |  62 +++++++++++++++-
 2 files changed, 81 insertions(+), 162 deletions(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 771d1e9..dd91383 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -8448,181 +8448,40 @@
   [(parallel
     [(set (match_operand:DSI 0 "register_operand" "")
           (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
-                        (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
+                        (match_operand:SI 2 "nonmemory_operand" "")))
      (clobber (reg:CC CC_REGNUM))])]
   ""
   "")
 
-(define_insn "*ashrdi3_cc_31"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
-                 (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=d")
-        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
-  "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
-  "srda\t%0,%Y2"
-  [(set_attr "op_type"  "RS")
-   (set_attr "atype"    "reg")])
-
-(define_insn "*ashrdi3_cconly_31"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-                              (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
-                 (const_int 0)))
-   (clobber (match_scratch:DI 0 "=d"))]
-  "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
-  "srda\t%0,%Y2"
-  [(set_attr "op_type"  "RS")
-   (set_attr "atype"    "reg")])
-
-(define_insn "*ashrdi3_31"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-        (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-                     (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
+; FIXME: The number of alternatives is doubled here to match the fix
+; number of 2 in the subst pattern for the (clobber (match_scratch...
+; The right fix should be to support match_scratch in the output
+; pattern of a define_subst.
+(define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
+  [(set (match_operand:DI 0 "register_operand"               "=d, d")
+        (ashiftrt:DI (match_operand:DI 1 "register_operand"   "0, 0")
+                     (match_operand:SI 2 "nonmemory_operand" "an,an")))
    (clobber (reg:CC CC_REGNUM))]
   "!TARGET_ZARCH"
-  "srda\t%0,%Y2"
-  [(set_attr "op_type"  "RS")
-   (set_attr "atype"    "reg")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cc"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
-                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
-                 (const_int 0)))
-   (set (match_operand:GPR 0 "register_operand"                                   "=d,d")
-        (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode(insn, CCSmode)"
   "@
-   sra<g>\t%0,<1>%Y2
-   sra<gk>\t%0,%1,%Y2"
-  [(set_attr "op_type"  "RS<E>,RSY")
-   (set_attr "atype"    "reg,reg")
-   (set_attr "cpu_facility" "*,z196")
-   (set_attr "z10prop" "z10_super_E1,*")])
+   srda\t%0,<addr_style_op_cc_ops>
+   srda\t%0,<addr_style_op_cc_ops>"
+  [(set_attr "op_type" "RS")
+   (set_attr "atype"   "reg")])
 
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cconly"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
-                               (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
-                 (const_int 0)))
-   (clobber (match_scratch:GPR 0                                                  "=d,d"))]
-  "s390_match_ccmode(insn, CCSmode)"
-  "@
-   sra<g>\t%0,<1>%Y2
-   sra<gk>\t%0,%1,%Y2"
-  [(set_attr "op_type"  "RS<E>,RSY")
-   (set_attr "atype"    "reg,reg")
-   (set_attr "cpu_facility" "*,z196")
-   (set_attr "z10prop" "z10_super_E1,*")])
 
 ; sra, srag
-(define_insn "*ashr<mode>3"
-  [(set (match_operand:GPR 0 "register_operand"                          "=d,d")
-        (ashiftrt:GPR (match_operand:GPR 1 "register_operand"          "<d0>,d")
-                      (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
+(define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
+  [(set (match_operand:GPR 0 "register_operand"                 "=d, d")
+        (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
+                      (match_operand:SI 2 "nonmemory_operand"   "an,an")))
    (clobber (reg:CC CC_REGNUM))]
   ""
   "@
-   sra<g>\t%0,<1>%Y2
-   sra<gk>\t%0,%1,%Y2"
-  [(set_attr "op_type"  "RS<E>,RSY")
-   (set_attr "atype"    "reg,reg")
-   (set_attr "cpu_facility" "*,z196")
-   (set_attr "z10prop" "z10_super_E1,*")])
-
-
-; shift pattern with implicit ANDs
-
-(define_insn "*ashrdi3_cc_31_and"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
-				      (match_operand:SI 3 "const_int_operand"   "n")))
-		 (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=d")
-        (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
-  "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
-   && (INTVAL (operands[3]) & 63) == 63"
-  "srda\t%0,%Y2"
-  [(set_attr "op_type"  "RS")
-   (set_attr "atype"    "reg")])
-
-(define_insn "*ashrdi3_cconly_31_and"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-                              (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
-				      (match_operand:SI 3 "const_int_operand"   "n")))
-                 (const_int 0)))
-   (clobber (match_scratch:DI 0 "=d"))]
-  "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
-   && (INTVAL (operands[3]) & 63) == 63"
-  "srda\t%0,%Y2"
-  [(set_attr "op_type"  "RS")
-   (set_attr "atype"    "reg")])
-
-(define_insn "*ashrdi3_31_and"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-        (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
-                     (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
-			     (match_operand:SI 3 "const_int_operand"   "n"))))
-   (clobber (reg:CC CC_REGNUM))]
-  "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
-  "srda\t%0,%Y2"
-  [(set_attr "op_type"  "RS")
-   (set_attr "atype"    "reg")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cc_and"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
-                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
-				       (match_operand:SI 3 "const_int_operand"             "n,n")))
-		 (const_int 0)))
-   (set (match_operand:GPR 0 "register_operand"                                           "=d,d")
-        (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
-  "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
-  "@
-   sra<g>\t%0,<1>%Y2
-   sra<gk>\t%0,%1,%Y2"
-  [(set_attr "op_type"  "RS<E>,RSY")
-   (set_attr "atype"    "reg,reg")
-   (set_attr "cpu_facility" "*,z196")
-   (set_attr "z10prop" "z10_super_E1,*")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cconly_and"
-  [(set (reg CC_REGNUM)
-        (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
-                               (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
-				       (match_operand:SI 3 "const_int_operand"             "n,n")))
-                 (const_int 0)))
-   (clobber (match_scratch:GPR 0                                                          "=d,d"))]
-  "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
-  "@
-   sra<g>\t%0,<1>%Y2
-   sra<gk>\t%0,%1,%Y2"
-  [(set_attr "op_type"  "RS<E>,RSY")
-   (set_attr "atype"    "reg,reg")
-   (set_attr "cpu_facility" "*,z196")
-   (set_attr "z10prop" "z10_super_E1,*")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_and"
-  [(set (match_operand:GPR 0 "register_operand"                                  "=d,d")
-        (ashiftrt:GPR (match_operand:GPR 1 "register_operand"                  "<d0>,d")
-                      (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
-			      (match_operand:SI 3 "const_int_operand"             "n,n"))))
-   (clobber (reg:CC CC_REGNUM))]
-  "(INTVAL (operands[3]) & 63) == 63"
-  "@
-   sra<g>\t%0,<1>%Y2
-   sra<gk>\t%0,%1,%Y2"
+   sra<g>\t%0,<1><addr_style_op_cc_ops>
+   sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
   [(set_attr "op_type"  "RS<E>,RSY")
-   (set_attr "atype"    "reg,reg")
+   (set_attr "atype"    "reg")
    (set_attr "cpu_facility" "*,z196")
    (set_attr "z10prop" "z10_super_E1,*")])
 
diff --git a/gcc/config/s390/subst.md b/gcc/config/s390/subst.md
index 907676a..3becf20 100644
--- a/gcc/config/s390/subst.md
+++ b/gcc/config/s390/subst.md
@@ -19,7 +19,7 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_code_iterator SUBST [rotate ashift lshiftrt])
+(define_code_iterator SUBST [rotate ashift lshiftrt ashiftrt])
 
 ; This expands an register/immediate operand to a register+immediate
 ; operand to draw advantage of the address style operand format
@@ -59,3 +59,63 @@
 ; Use this in the insn name.
 (define_subst_attr "masked_op" "masked_op_subst" "" "_and")
 
+
+
+; This is like the addr_style_op substitution above but with a CC clobber.
+(define_subst "addr_style_op_cc_subst"
+  [(set (match_operand:DSI 0 ""           "")
+        (ashiftrt:DSI (match_operand:DSI 1 "" "")
+		      (match_operand:SI 2 "" "")))
+   (clobber (reg:CC CC_REGNUM))]
+  "REG_P (operands[2])"
+  [(set (match_dup 0)
+        (ashiftrt:DSI (match_dup 1)
+		      (plus:SI (match_dup 2)
+			       (match_operand 3 "const_int_operand" "n"))))
+   (clobber (reg:CC CC_REGNUM))])
+
+(define_subst_attr "addr_style_op_cc"     "addr_style_op_cc_subst" "" "_plus")
+(define_subst_attr "addr_style_op_cc_ops" "addr_style_op_cc_subst" "%Y2" "%Y3(%2)")
+
+
+; This is like the masked_op substitution but with a CC clobber.
+(define_subst "masked_op_cc_subst"
+  [(set (match_operand:DSI 0 ""           "")
+        (ashiftrt:DSI (match_operand:DSI 1 "" "")
+		      (match_operand:SI  2 "" "")))
+   (clobber (reg:CC CC_REGNUM))]
+  ""
+  [(set (match_dup 0)
+        (ashiftrt:DSI (match_dup 1)
+		      (and:SI (match_dup 2)
+			      (match_operand:SI 3 "const_int_6bitset_operand" ""))))
+   (clobber (reg:CC CC_REGNUM))])
+(define_subst_attr "masked_op_cc" "masked_op_cc_subst" "" "_and")
+
+
+; This adds an explicit CC reg set to an operation while keeping the
+; set for the operation result as well.
+(define_subst "setcc_subst"
+  [(set (match_operand:DSI 0 ""           "")
+        (match_operand:DSI 1 "" ""))
+   (clobber (reg:CC CC_REGNUM))]
+  "s390_match_ccmode(insn, CCSmode)"
+  [(set (reg CC_REGNUM)
+	(compare (match_dup 1) (const_int 0)))
+   (set (match_dup 0) (match_dup 1))])
+
+; Use this in the insn name.
+(define_subst_attr "setcc" "setcc_subst" "" "_cc")
+
+; This adds an explicit CC reg set to an operation while dropping the
+; result of the operation.
+(define_subst "cconly_subst"
+  [(set (match_operand:DSI 0 ""           "")
+        (match_operand:DSI 1 "" ""))
+   (clobber (reg:CC CC_REGNUM))]
+  "s390_match_ccmode(insn, CCSmode)"
+  [(set (reg CC_REGNUM)
+	(compare (match_dup 1) (const_int 0)))
+   (clobber (match_scratch:DSI 0 "=d,d"))])
+
+(define_subst_attr "cconly" "cconly_subst" "" "_cconly")
-- 
1.9.1

[PATCH 0/9] S/390 rework shift count handling - v3

[Andreas Krebbel]

here is an updated version of the shift count rework in the S/390
backend.

Bootstrapped and regtested on s390 and s390x --with-arch=z196,zEC12,z13

Changes:

- Merge the address reg and immediate alternatives as suggested in:
  https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01744.html

- Add constraints (jm6 and jm8) equivalent to the
  const_int_6bitset_operand and const_int_8bitset_operand predicates.

Andreas Krebbel (9):
  gensupport: Fix define_subst operand renumbering.
  S/390: Use enabled attribute overrides to disable alternatives.
  S/390: Get rid of Y constraint in rotate patterns.
  S/390: Get rid of Y constraint in left and logical right shift
    patterns.
  S/390: Get rid of Y constraint in arithmetic right shift patterns.
  S/390: Get rid of Y constraint in tabort.
  S/390: Get rid of Y constraint in vector.md.
  S/390: Use define_subst for the setmem patterns.
  S/390: Disallow SImode in s390_decompose_address

 gcc/config/s390/constraints.md |   9 +
 gcc/config/s390/predicates.md  |  10 +
 gcc/config/s390/s390.c         |  31 ++-
 gcc/config/s390/s390.md        | 530 ++++++++++++++---------------------------
 gcc/config/s390/subst.md       | 147 ++++++++++++
 gcc/config/s390/vector.md      | 127 +++++-----
 gcc/gensupport.c               |  45 ++--
 7 files changed, 453 insertions(+), 446 deletions(-)
 create mode 100644 gcc/config/s390/subst.md

-- 
1.9.1

[PATCH 6/9] S/390: Get rid of Y constraint in tabort.

[Andreas Krebbel]

This removes the Y constraint from the tabort pattern definition.  In
this case it is easier without using substitutions.

gcc/ChangeLog:

2016-02-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.md ("*tabort_1"): Change predicate to
	nonmemory_operand.  Add a second alternative to cover
	register as well as const int operands.
	("*tabort_1_plus"): New pattern definition.
---
 gcc/config/s390/s390.md | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index dd91383..ca58c42 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -10698,7 +10698,7 @@
 ; Transaction abort
 
 (define_expand "tabort"
-  [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
+  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
 		    UNSPECV_TABORT)]
   "TARGET_HTM && operands != NULL"
 {
@@ -10713,12 +10713,21 @@
 })
 
 (define_insn "*tabort_1"
-  [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
+  [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
 		    UNSPECV_TABORT)]
   "TARGET_HTM && operands != NULL"
   "tabort\t%Y0"
   [(set_attr "op_type" "S")])
 
+(define_insn "*tabort_1_plus"
+  [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand"  "a")
+			      (match_operand:SI 1 "const_int_operand" "J"))]
+		    UNSPECV_TABORT)]
+  "TARGET_HTM && operands != NULL
+   && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
+  "tabort\t%1(%0)"
+  [(set_attr "op_type" "S")])
+
 ; Transaction extract nesting depth
 
 (define_insn "etnd"
-- 
1.9.1

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[Bernd Schmidt]

On 02/29/2016 09:46 AM, Andreas Krebbel wrote:
> Ok for mainline?
>
> 	* gensupport.c (process_substs_on_one_elem): Split loop to
> 	complete mark_operands_used_in_match_dup on all expressions in the
> 	vector first.
> 	(adjust_operands_numbers): Inline into process_substs_on_one_elem
> 	and remove function.

Didn't I approve this a while ago? Not sure it's appropriate for stage4 
though; is this series fixing an important regression?


Bernd

Re: [PATCH 7/9] S/390: Get rid of Y constraint in vector.md.

[Ulrich Weigand]

Andreas Krebbel wrote:


> +; vec_set is supposed to *modify* an existing vector so operand 0 is
> +; duplicated as input operand.
> +(define_expand "vec_set<mode>"
> +  [(set (match_operand:V                    0 "register_operand"              "")
> +	(unspec:V [(match_operand:<non_vec> 1 "general_operand"               "")
> +		   (match_operand:SI        2 "shift_count_or_setmem_operand" "")

This is probably only cosmetic, but should we use nonmemory_operand here
instead of shift_count_or_setmem_operand (just like everywhere else now)?

> +(define_expand "vec_extract<mode>"
> +  [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "")
> +	(unspec:<non_vec> [(match_operand:V  1 "register_operand" "")
> +			   (match_operand:SI 2 "shift_count_or_setmem_operand" "")]

Likewise.


> +(define_insn "*vec_set<mode>_plus"
> +  [(set (match_operand:V                      0 "register_operand" "=v")
> +	(unspec:V [(match_operand:<non_vec>   1 "general_operand"   "d")
> +		   (plus:SI (match_operand:SI 2 "register_operand"  "a")
> +			    (match_operand:SI 4 "const_int_operand" "n"))
> +		   (match_operand:V           3 "register_operand"  "0")]
> +		  UNSPEC_VEC_SET))]
> +  "TARGET_VX"
> +  "vlvg<bhfgq>\t%v0,%1,%4(%2)"
> +  [(set_attr "op_type" "VRS")])

Wouldn't it be better to use %Y4 instead of %4 here?  Or does the middle-end
guarantee that this is never out of range?

> +(define_insn "*vec_extract<mode>_plus"
> +  [(set (match_operand:<non_vec>                      0 "nonimmediate_operand" "=d,QR")
> +	(unspec:<non_vec> [(match_operand:V           1 "register_operand"      "v, v")
> +			   (plus:SI (match_operand:SI 2 "nonmemory_operand"     "a, I")
> +				    (match_operand:SI 3 "const_int_operand"     "n, I"))]
> +			   UNSPEC_VEC_EXTRACT))]
> +  "TARGET_VX"
> +  "@
> +   vlgv<bhfgq>\t%0,%v1,%3(%2)
> +   vste<bhfgq>\t%v1,%0,%2"
> +  [(set_attr "op_type" "VRS,VRX")])

Likewise for %3.  Also, the second alternative seems odd, it matches solely a
PLUS of two CONST_INTs, which is not canonical RTL ...

Bye,
Ulrich

-- 
  Dr. Ulrich Weigand
  GNU/Linux compilers and toolchain
  Ulrich.Weigand@de.ibm.com

Re: [PATCH 0/9] S/390 rework shift count handling - v3

[Ulrich Weigand]

Andreas Krebbel wrote:

>   S/390: Use enabled attribute overrides to disable alternatives.
>   S/390: Get rid of Y constraint in rotate patterns.
>   S/390: Get rid of Y constraint in left and logical right shift
>     patterns.
>   S/390: Get rid of Y constraint in arithmetic right shift patterns.
>   S/390: Get rid of Y constraint in tabort.
>   S/390: Get rid of Y constraint in vector.md.
>   S/390: Use define_subst for the setmem patterns.
>   S/390: Disallow SImode in s390_decompose_address

Except for a few minor comments for the vector.md patch (separate mail),
this all looks now very good to me.

Thanks,
Ulrich

-- 
  Dr. Ulrich Weigand
  GNU/Linux compilers and toolchain
  Ulrich.Weigand@de.ibm.com

Re: [PATCH 0/9] S/390 rework shift count handling - v3

[Andreas Krebbel]

On 02/29/2016 03:58 PM, Ulrich Weigand wrote:
> Andreas Krebbel wrote:
> 
>>   S/390: Use enabled attribute overrides to disable alternatives.
>>   S/390: Get rid of Y constraint in rotate patterns.
>>   S/390: Get rid of Y constraint in left and logical right shift
>>     patterns.
>>   S/390: Get rid of Y constraint in arithmetic right shift patterns.
>>   S/390: Get rid of Y constraint in tabort.
>>   S/390: Get rid of Y constraint in vector.md.
>>   S/390: Use define_subst for the setmem patterns.
>>   S/390: Disallow SImode in s390_decompose_address
> 
> Except for a few minor comments for the vector.md patch (separate mail),
> this all looks now very good to me.

Ok. Thanks! I've committed the patches now with the last changes you proposed.

-Andreas-

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[Andreas Krebbel]

On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
> On 02/29/2016 09:46 AM, Andreas Krebbel wrote:
>> Ok for mainline?
>>
>> 	* gensupport.c (process_substs_on_one_elem): Split loop to
>> 	complete mark_operands_used_in_match_dup on all expressions in the
>> 	vector first.
>> 	(adjust_operands_numbers): Inline into process_substs_on_one_elem
>> 	and remove function.
> 
> Didn't I approve this a while ago? Not sure it's appropriate for stage4 
> though; is this series fixing an important regression?

Yes you did. I didn't commit it until the rest of the patch series was ready to commit.  The patch
series fixes a fundamental problem in the backend. The first iteration was posted before stage 4 but
it took me a few iterations to get it right.

I've committed the patch now after retesting.

-Andreas-

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[James Greenhalgh]

On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote:
> On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
> > On 02/29/2016 09:46 AM, Andreas Krebbel wrote:
> >> Ok for mainline?
> >>
> >> 	* gensupport.c (process_substs_on_one_elem): Split loop to
> >> 	complete mark_operands_used_in_match_dup on all expressions in the
> >> 	vector first.
> >> 	(adjust_operands_numbers): Inline into process_substs_on_one_elem
> >> 	and remove function.
> > 
> > Didn't I approve this a while ago? Not sure it's appropriate for stage4 
> > though; is this series fixing an important regression?
> 
> Yes you did. I didn't commit it until the rest of the patch series was ready to commit.  The patch
> series fixes a fundamental problem in the backend. The first iteration was posted before stage 4 but
> it took me a few iterations to get it right.
> 
> I've committed the patch now after retesting.

This looks like it has caused failures in the following tests on an
x86_64-none-linux-gnu build.

The failures are of this form:

In file included from /data/work/gcc-bisect-bot/build/gcc/include/immintrin.h:45:0,
                 from /work/gcc-bisect-bot/gcc/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-1.c:12:
/data/work/gcc-bisect-bot/build/gcc/include/avx512fintrin.h: In function 'avx512f_test':
/data/work/gcc-bisect-bot/build/gcc/include/avx512fintrin.h:11666:10: internal compiler error: Segmentation fault
0xb1a18f crash_signal
	/work/gcc-bisect-bot/gcc/gcc/toplev.c:335
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <http://gcc.gnu.org/bugs.html> for instructions.

There are lots of them, so I'm just mentioning the unique names below.

  gcc.target/i386/avx512f-vfmaddsubXXXps-2.c
  gcc.target/i386/avx512f-vfmsubaddXXXps-2.c
  gcc.target/i386/avx512f-vfnmsubXXXps-2.c
  gcc.target/i386/avx512f-vfnmsubXXXps-1.c
  gcc.target/i386/avx-2.c
  gcc.target/i386/avx512vl-vshufpd-1.c
  gcc.target/i386/avx512f-vfmsubXXXpd-2.c
  gcc.target/i386/avx-1.c
  gcc.target/i386/avx512f-vfixupimmsd-1.c
  gcc.target/i386/avx512f-vfmsubXXXps-1.c
  gcc.target/i386/avx512f-vfmsubaddXXXpd-2.c
  gcc.target/i386/avx512f-vfmsubXXXps-2.c
  gcc.target/i386/avx512vl-vshufps-1.c
  gcc.target/i386/avx512f-vfmaddsubXXXps-1.c
  gcc.target/i386/avx512f-vfixupimmsd-2.c
  gcc.target/i386/avx512f-vfmaddXXXps-1.c
  gcc.target/i386/avx512f-vfmaddsubXXXpd-1.c
  gcc.target/i386/avx512f-vfmaddXXXpd-2.c
  gcc.target/i386/avx512f-vfmaddXXXps-2.c
  gcc.target/i386/avx512f-vfmaddsubXXXpd-2.c
  gcc.target/i386/sse-22.c
  gcc.target/i386/avx512f-vfmsubXXXpd-1.c
  gcc.target/i386/testround-1.c
  gcc.target/i386/sse-23.c
  gcc.target/i386/avx512f-vfmsubaddXXXpd-1.c
  gcc.target/i386/sse-22a.c
  gcc.target/i386/sse-25.c
  gcc.target/i386/sse-24.c
  gcc.target/i386/avx512f-vfnmsubXXXpd-2.c
  gcc.target/i386/sse-14.c
  gcc.target/i386/avx512f-vfixupimmss-1.c
  gcc.target/i386/avx512f-vfnmaddXXXpd-1.c
  gcc.target/i386/avx512f-vfnmaddXXXps-2.c
  gcc.target/i386/avx512f-vfixupimmpd-2.c
  gcc.target/i386/avx512f-vfnmaddXXXpd-2.c
  gcc.target/i386/sse-13.c
  gcc.target/i386/avx512f-vfixupimmps-1.c
  gcc.target/i386/avx512f-vfnmsubXXXpd-1.c
  gcc.target/i386/avx512f-vfnmaddXXXps-1.c
  gcc.target/i386/avx512f-vfixupimmps-2.c
  gcc.target/i386/avx512f-vfmaddXXXpd-1.c
  gcc.target/i386/testimm-10.c
  gcc.target/i386/avx512f-vfmsubaddXXXps-1.c
  gcc.target/i386/avx512f-vfixupimmss-2.c
  gcc.target/i386/avx512f-vfixupimmpd-1.c

Author: krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4>
Date:   Tue Mar 1 09:19:14 2016 +0000

    gensupport: Fix define_subst operand renumbering.
    
    When processing substitutions the operands are renumbered.  To find a
    free operand number the array used_operands_numbers is used.
    Currently this array is used to assign new numbers before all the
    RTXes in the vector have been processed.  I did run into problems with
    this for insns where a match_dup occurred in a later (use ...) operand
    referring to an earlier operand (e.g. s390.md "setmem_long").
    
    The patch splits the loop doing the processing into two in order to
    have all the operand numbers collected already when assigning new
    numbers.
    
    gcc/ChangeLog:
    
    2016-03-01  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
    
    	* gensupport.c (process_substs_on_one_elem): Split loop to
    	complete mark_operands_used_in_match_dup on all expressions in the
    	vector first.
    	(adjust_operands_numbers): Inline into process_substs_on_one_elem
    	and remove function.

svn+ssh://gcc.gnu.org/svn/gcc/trunk@233841

Thanks,
James

> 
> -Andreas-
> 

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[Bernd Schmidt]

On 03/01/2016 01:15 PM, James Greenhalgh wrote:
> On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote:
>> On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
>>> Didn't I approve this a while ago? Not sure it's appropriate for stage4
>>> though; is this series fixing an important regression?
>>
>> Yes you did. I didn't commit it until the rest of the patch series was ready to commit.  The patch
>> series fixes a fundamental problem in the backend. The first iteration was posted before stage 4 but
>> it took me a few iterations to get it right.
>>
>> I've committed the patch now after retesting.
>
> This looks like it has caused failures in the following tests on an
> x86_64-none-linux-gnu build.

My inclination would be not to change this code in stage4, it looks too 
fragile.


Bernd

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[Andreas Krebbel]

On 03/01/2016 01:15 PM, James Greenhalgh wrote:
> On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote:
>> On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
>>> On 02/29/2016 09:46 AM, Andreas Krebbel wrote:
>>>> Ok for mainline?
>>>>
>>>> 	* gensupport.c (process_substs_on_one_elem): Split loop to
>>>> 	complete mark_operands_used_in_match_dup on all expressions in the
>>>> 	vector first.
>>>> 	(adjust_operands_numbers): Inline into process_substs_on_one_elem
>>>> 	and remove function.
>>>
>>> Didn't I approve this a while ago? Not sure it's appropriate for stage4 
>>> though; is this series fixing an important regression?
>>
>> Yes you did. I didn't commit it until the rest of the patch series was ready to commit.  The patch
>> series fixes a fundamental problem in the backend. The first iteration was posted before stage 4 but
>> it took me a few iterations to get it right.
>>
>> I've committed the patch now after retesting.
> 
> This looks like it has caused failures in the following tests on an
> x86_64-none-linux-gnu build.

I've regression tested the patch on x86_64 as well.  Are there specific options required to enable
these tests?

Sorry for the breakage. I'll revert the patch together with the affected parts of my S/390 patchset.
I'll just need a couple of hours to re-test on S/390.

Bye,

-Andreas-

> 
> The failures are of this form:
> 
> In file included from /data/work/gcc-bisect-bot/build/gcc/include/immintrin.h:45:0,
>                  from /work/gcc-bisect-bot/gcc/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-1.c:12:
> /data/work/gcc-bisect-bot/build/gcc/include/avx512fintrin.h: In function 'avx512f_test':
> /data/work/gcc-bisect-bot/build/gcc/include/avx512fintrin.h:11666:10: internal compiler error: Segmentation fault
> 0xb1a18f crash_signal
> 	/work/gcc-bisect-bot/gcc/gcc/toplev.c:335
> Please submit a full bug report,
> with preprocessed source if appropriate.
> Please include the complete backtrace with any bug report.
> See <http://gcc.gnu.org/bugs.html> for instructions.
> 
> There are lots of them, so I'm just mentioning the unique names below.
> 
>   gcc.target/i386/avx512f-vfmaddsubXXXps-2.c
>   gcc.target/i386/avx512f-vfmsubaddXXXps-2.c
>   gcc.target/i386/avx512f-vfnmsubXXXps-2.c
>   gcc.target/i386/avx512f-vfnmsubXXXps-1.c
>   gcc.target/i386/avx-2.c
>   gcc.target/i386/avx512vl-vshufpd-1.c
>   gcc.target/i386/avx512f-vfmsubXXXpd-2.c
>   gcc.target/i386/avx-1.c
>   gcc.target/i386/avx512f-vfixupimmsd-1.c
>   gcc.target/i386/avx512f-vfmsubXXXps-1.c
>   gcc.target/i386/avx512f-vfmsubaddXXXpd-2.c
>   gcc.target/i386/avx512f-vfmsubXXXps-2.c
>   gcc.target/i386/avx512vl-vshufps-1.c
>   gcc.target/i386/avx512f-vfmaddsubXXXps-1.c
>   gcc.target/i386/avx512f-vfixupimmsd-2.c
>   gcc.target/i386/avx512f-vfmaddXXXps-1.c
>   gcc.target/i386/avx512f-vfmaddsubXXXpd-1.c
>   gcc.target/i386/avx512f-vfmaddXXXpd-2.c
>   gcc.target/i386/avx512f-vfmaddXXXps-2.c
>   gcc.target/i386/avx512f-vfmaddsubXXXpd-2.c
>   gcc.target/i386/sse-22.c
>   gcc.target/i386/avx512f-vfmsubXXXpd-1.c
>   gcc.target/i386/testround-1.c
>   gcc.target/i386/sse-23.c
>   gcc.target/i386/avx512f-vfmsubaddXXXpd-1.c
>   gcc.target/i386/sse-22a.c
>   gcc.target/i386/sse-25.c
>   gcc.target/i386/sse-24.c
>   gcc.target/i386/avx512f-vfnmsubXXXpd-2.c
>   gcc.target/i386/sse-14.c
>   gcc.target/i386/avx512f-vfixupimmss-1.c
>   gcc.target/i386/avx512f-vfnmaddXXXpd-1.c
>   gcc.target/i386/avx512f-vfnmaddXXXps-2.c
>   gcc.target/i386/avx512f-vfixupimmpd-2.c
>   gcc.target/i386/avx512f-vfnmaddXXXpd-2.c
>   gcc.target/i386/sse-13.c
>   gcc.target/i386/avx512f-vfixupimmps-1.c
>   gcc.target/i386/avx512f-vfnmsubXXXpd-1.c
>   gcc.target/i386/avx512f-vfnmaddXXXps-1.c
>   gcc.target/i386/avx512f-vfixupimmps-2.c
>   gcc.target/i386/avx512f-vfmaddXXXpd-1.c
>   gcc.target/i386/testimm-10.c
>   gcc.target/i386/avx512f-vfmsubaddXXXps-1.c
>   gcc.target/i386/avx512f-vfixupimmss-2.c
>   gcc.target/i386/avx512f-vfixupimmpd-1.c
> 
> Author: krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4>
> Date:   Tue Mar 1 09:19:14 2016 +0000
> 
>     gensupport: Fix define_subst operand renumbering.
>     
>     When processing substitutions the operands are renumbered.  To find a
>     free operand number the array used_operands_numbers is used.
>     Currently this array is used to assign new numbers before all the
>     RTXes in the vector have been processed.  I did run into problems with
>     this for insns where a match_dup occurred in a later (use ...) operand
>     referring to an earlier operand (e.g. s390.md "setmem_long").
>     
>     The patch splits the loop doing the processing into two in order to
>     have all the operand numbers collected already when assigning new
>     numbers.
>     
>     gcc/ChangeLog:
>     
>     2016-03-01  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
>     
>     	* gensupport.c (process_substs_on_one_elem): Split loop to
>     	complete mark_operands_used_in_match_dup on all expressions in the
>     	vector first.
>     	(adjust_operands_numbers): Inline into process_substs_on_one_elem
>     	and remove function.
> 
> svn+ssh://gcc.gnu.org/svn/gcc/trunk@233841
> 
> Thanks,
> James
> 
>>
>> -Andreas-
>>
> 

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[James Greenhalgh]

On Tue, Mar 01, 2016 at 01:35:18PM +0100, Andreas Krebbel wrote:
> On 03/01/2016 01:15 PM, James Greenhalgh wrote:
> > On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote:
> >> On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
> >>> On 02/29/2016 09:46 AM, Andreas Krebbel wrote:
> >>>> Ok for mainline?
> >>>>
> >>>> 	* gensupport.c (process_substs_on_one_elem): Split loop to
> >>>> 	complete mark_operands_used_in_match_dup on all expressions in the
> >>>> 	vector first.
> >>>> 	(adjust_operands_numbers): Inline into process_substs_on_one_elem
> >>>> 	and remove function.
> >>>
> >>> Didn't I approve this a while ago? Not sure it's appropriate for stage4 
> >>> though; is this series fixing an important regression?
> >>
> >> Yes you did. I didn't commit it until the rest of the patch series was ready to commit.  The patch
> >> series fixes a fundamental problem in the backend. The first iteration was posted before stage 4 but
> >> it took me a few iterations to get it right.
> >>
> >> I've committed the patch now after retesting.
> > 
> > This looks like it has caused failures in the following tests on an
> > x86_64-none-linux-gnu build.
> 
> I've regression tested the patch on x86_64 as well.  Are there specific
> options required to enable these tests?

The bisect robot just builds a stage one compiler, configured with:

  ./configure --disable-bootstrap, --enable-languages=c,c++,fortran
              --disable-multilib --disable-libsanitizer

My system GCC is a 5.2 from the release sources with:

  ../gcc-5.2.0/configure --with-bugurl='Good luck'
                         --enable-languages=c,c++,go,fortran,objc,obj-c++
                         --prefix=/work/install-gcc-5.2.0 --enable-shared
                         --enable-linker-build-id --without-included-gettext
                         --enable-threads=posix --enable-nls
			 --enable-clocale=gnu --enable-libstdcxx-debug
                         --enable-libstdcxx-time=yes
                         --enable-gnu-unique-object --disable-libmudflap
                         --enable-plugin --with-system-zlib
                         --disable-browser-plugin --enable-java-awt=gtk
                         --enable-gtk-cairo --with-arch-directory=amd64
                         --enable-objc-gc --enable-multiarch
                         --disable-werror --with-arch-32=i686
                         --with-abi=m64 --with-multilib-list=m32,m64,mx32
                         --with-tune=native --enable-checking=release
                         --build=x86_64-linux-gnu --host=x86_64-linux-gnu
                         --target=x86_64-linux-gnu

I tried a full bootstrap at that revision and still see these failures.
Who knows what state has been corrupted, or that you silently get away with,
if this is an undefined behaviour somewhere :-). I haven't tried with a
valgrind checking build to see what it can spot.

Thanks,
James

> > 
> > The failures are of this form:
> > 
> > In file included from /data/work/gcc-bisect-bot/build/gcc/include/immintrin.h:45:0,
> >                  from /work/gcc-bisect-bot/gcc/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-1.c:12:
> > /data/work/gcc-bisect-bot/build/gcc/include/avx512fintrin.h: In function 'avx512f_test':
> > /data/work/gcc-bisect-bot/build/gcc/include/avx512fintrin.h:11666:10: internal compiler error: Segmentation fault
> > 0xb1a18f crash_signal
> > 	/work/gcc-bisect-bot/gcc/gcc/toplev.c:335
> > Please submit a full bug report,
> > with preprocessed source if appropriate.
> > Please include the complete backtrace with any bug report.
> > See <http://gcc.gnu.org/bugs.html> for instructions.
> > 
> > There are lots of them, so I'm just mentioning the unique names below.
> > 
> >   gcc.target/i386/avx512f-vfmaddsubXXXps-2.c
> >   gcc.target/i386/avx512f-vfmsubaddXXXps-2.c
> >   gcc.target/i386/avx512f-vfnmsubXXXps-2.c
> >   gcc.target/i386/avx512f-vfnmsubXXXps-1.c
> >   gcc.target/i386/avx-2.c
> >   gcc.target/i386/avx512vl-vshufpd-1.c
> >   gcc.target/i386/avx512f-vfmsubXXXpd-2.c
> >   gcc.target/i386/avx-1.c
> >   gcc.target/i386/avx512f-vfixupimmsd-1.c
> >   gcc.target/i386/avx512f-vfmsubXXXps-1.c
> >   gcc.target/i386/avx512f-vfmsubaddXXXpd-2.c
> >   gcc.target/i386/avx512f-vfmsubXXXps-2.c
> >   gcc.target/i386/avx512vl-vshufps-1.c
> >   gcc.target/i386/avx512f-vfmaddsubXXXps-1.c
> >   gcc.target/i386/avx512f-vfixupimmsd-2.c
> >   gcc.target/i386/avx512f-vfmaddXXXps-1.c
> >   gcc.target/i386/avx512f-vfmaddsubXXXpd-1.c
> >   gcc.target/i386/avx512f-vfmaddXXXpd-2.c
> >   gcc.target/i386/avx512f-vfmaddXXXps-2.c
> >   gcc.target/i386/avx512f-vfmaddsubXXXpd-2.c
> >   gcc.target/i386/sse-22.c
> >   gcc.target/i386/avx512f-vfmsubXXXpd-1.c
> >   gcc.target/i386/testround-1.c
> >   gcc.target/i386/sse-23.c
> >   gcc.target/i386/avx512f-vfmsubaddXXXpd-1.c
> >   gcc.target/i386/sse-22a.c
> >   gcc.target/i386/sse-25.c
> >   gcc.target/i386/sse-24.c
> >   gcc.target/i386/avx512f-vfnmsubXXXpd-2.c
> >   gcc.target/i386/sse-14.c
> >   gcc.target/i386/avx512f-vfixupimmss-1.c
> >   gcc.target/i386/avx512f-vfnmaddXXXpd-1.c
> >   gcc.target/i386/avx512f-vfnmaddXXXps-2.c
> >   gcc.target/i386/avx512f-vfixupimmpd-2.c
> >   gcc.target/i386/avx512f-vfnmaddXXXpd-2.c
> >   gcc.target/i386/sse-13.c
> >   gcc.target/i386/avx512f-vfixupimmps-1.c
> >   gcc.target/i386/avx512f-vfnmsubXXXpd-1.c
> >   gcc.target/i386/avx512f-vfnmaddXXXps-1.c
> >   gcc.target/i386/avx512f-vfixupimmps-2.c
> >   gcc.target/i386/avx512f-vfmaddXXXpd-1.c
> >   gcc.target/i386/testimm-10.c
> >   gcc.target/i386/avx512f-vfmsubaddXXXps-1.c
> >   gcc.target/i386/avx512f-vfixupimmss-2.c
> >   gcc.target/i386/avx512f-vfixupimmpd-1.c
> > 
> > Author: krebbel <krebbel@138bc75d-0d04-0410-961f-82ee72b054a4>
> > Date:   Tue Mar 1 09:19:14 2016 +0000
> > 
> >     gensupport: Fix define_subst operand renumbering.
> >     
> >     When processing substitutions the operands are renumbered.  To find a
> >     free operand number the array used_operands_numbers is used.
> >     Currently this array is used to assign new numbers before all the
> >     RTXes in the vector have been processed.  I did run into problems with
> >     this for insns where a match_dup occurred in a later (use ...) operand
> >     referring to an earlier operand (e.g. s390.md "setmem_long").
> >     
> >     The patch splits the loop doing the processing into two in order to
> >     have all the operand numbers collected already when assigning new
> >     numbers.
> >     
> >     gcc/ChangeLog:
> >     
> >     2016-03-01  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
> >     
> >     	* gensupport.c (process_substs_on_one_elem): Split loop to
> >     	complete mark_operands_used_in_match_dup on all expressions in the
> >     	vector first.
> >     	(adjust_operands_numbers): Inline into process_substs_on_one_elem
> >     	and remove function.
> > 
> > svn+ssh://gcc.gnu.org/svn/gcc/trunk@233841
> > 
> > Thanks,
> > James
> > 
> >>
> >> -Andreas-
> >>
> > 
> 

Re: [PATCH 1/9] gensupport: Fix define_subst operand renumbering.

[Andreas Krebbel]

On 03/01/2016 02:38 PM, James Greenhalgh wrote:
> On Tue, Mar 01, 2016 at 01:35:18PM +0100, Andreas Krebbel wrote:
>> On 03/01/2016 01:15 PM, James Greenhalgh wrote:
>>> On Tue, Mar 01, 2016 at 10:29:28AM +0100, Andreas Krebbel wrote:
>>>> On 02/29/2016 02:36 PM, Bernd Schmidt wrote:
>>>>> On 02/29/2016 09:46 AM, Andreas Krebbel wrote:
>>>>>> Ok for mainline?
>>>>>>
>>>>>> 	* gensupport.c (process_substs_on_one_elem): Split loop to
>>>>>> 	complete mark_operands_used_in_match_dup on all expressions in the
>>>>>> 	vector first.
>>>>>> 	(adjust_operands_numbers): Inline into process_substs_on_one_elem
>>>>>> 	and remove function.
>>>>>
>>>>> Didn't I approve this a while ago? Not sure it's appropriate for stage4 
>>>>> though; is this series fixing an important regression?
>>>>
>>>> Yes you did. I didn't commit it until the rest of the patch series was ready to commit.  The patch
>>>> series fixes a fundamental problem in the backend. The first iteration was posted before stage 4 but
>>>> it took me a few iterations to get it right.
>>>>
>>>> I've committed the patch now after retesting.
>>>
>>> This looks like it has caused failures in the following tests on an
>>> x86_64-none-linux-gnu build.
>>
>> I've regression tested the patch on x86_64 as well.  Are there specific
>> options required to enable these tests?
> 
> The bisect robot just builds a stage one compiler, configured with:
> 
>   ./configure --disable-bootstrap, --enable-languages=c,c++,fortran
>               --disable-multilib --disable-libsanitizer
> 
> My system GCC is a 5.2 from the release sources with:
> 
>   ../gcc-5.2.0/configure --with-bugurl='Good luck'
>                          --enable-languages=c,c++,go,fortran,objc,obj-c++
>                          --prefix=/work/install-gcc-5.2.0 --enable-shared
>                          --enable-linker-build-id --without-included-gettext
>                          --enable-threads=posix --enable-nls
> 			 --enable-clocale=gnu --enable-libstdcxx-debug
>                          --enable-libstdcxx-time=yes
>                          --enable-gnu-unique-object --disable-libmudflap
>                          --enable-plugin --with-system-zlib
>                          --disable-browser-plugin --enable-java-awt=gtk
>                          --enable-gtk-cairo --with-arch-directory=amd64
>                          --enable-objc-gc --enable-multiarch
>                          --disable-werror --with-arch-32=i686
>                          --with-abi=m64 --with-multilib-list=m32,m64,mx32
>                          --with-tune=native --enable-checking=release
>                          --build=x86_64-linux-gnu --host=x86_64-linux-gnu
>                          --target=x86_64-linux-gnu
> 
> I tried a full bootstrap at that revision and still see these failures.
> Who knows what state has been corrupted, or that you silently get away with,
> if this is an undefined behaviour somewhere :-). I haven't tried with a
> valgrind checking build to see what it can spot.

Ok. Thanks for the infos.  I'll try to have a look. I've reverted the patch now.

Bye,

-Andreas-

Re: [PATCH 7/9] S/390: Get rid of Y constraint in vector.md.

[Ulrich Weigand]

I wrote:
> Andreas Krebbel wrote:
> 
> > +; vec_set is supposed to *modify* an existing vector so operand 0 is
> > +; duplicated as input operand.
> > +(define_expand "vec_set<mode>"
> > +  [(set (match_operand:V                    0 "register_operand"              "")
> > +	(unspec:V [(match_operand:<non_vec> 1 "general_operand"               "")
> > +		   (match_operand:SI        2 "shift_count_or_setmem_operand" "")
> 
> This is probably only cosmetic, but should we use nonmemory_operand here
> instead of shift_count_or_setmem_operand (just like everywhere else now)?
> 
> > +(define_expand "vec_extract<mode>"
> > +  [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "")
> > +	(unspec:<non_vec> [(match_operand:V  1 "register_operand" "")
> > +			   (match_operand:SI 2 "shift_count_or_setmem_operand" "")]
> 
> Likewise.

I just noticed that there are two more UNSPEC_VEC_SET expanders
in vx-builtins.md.  I guess those should be likewise changed:

(define_expand "vec_insert<mode>"
  [(set (match_operand:V_HW                    0 "register_operand" "")
        (unspec:V_HW [(match_operand:<non_vec> 2 "register_operand" "")
                      (match_operand:SI        3 "shift_count_or_setmem_operand" "")
                      (match_operand:V_HW      1 "register_operand" "")]
                     UNSPEC_VEC_SET))]
  "TARGET_VX"
  "")

(define_expand "vec_promote<mode>"
  [(set (match_operand:V_HW                    0 "register_operand" "")
        (unspec:V_HW [(match_operand:<non_vec> 1 "register_operand" "")
                      (match_operand:SI        2 "shift_count_or_setmem_operand" "")
                      (match_dup 0)]
                     UNSPEC_VEC_SET))]
  "TARGET_VX"
  "")

Then the only remaining users of shift_count_or_setmem_operand are the
actual setmem patterns (so maybe the predicate can be renamed to
"setmem_operand") :-)

Bye,
Ulrich

-- 
  Dr. Ulrich Weigand
  GNU/Linux compilers and toolchain
  Ulrich.Weigand@de.ibm.com

Re: [PATCH 7/9] S/390: Get rid of Y constraint in vector.md.

[Andreas Krebbel]

On 03/01/2016 04:11 PM, Ulrich Weigand wrote:
> I wrote:
>> Andreas Krebbel wrote:
>>
>>> +; vec_set is supposed to *modify* an existing vector so operand 0 is
>>> +; duplicated as input operand.
>>> +(define_expand "vec_set<mode>"
>>> +  [(set (match_operand:V                    0 "register_operand"              "")
>>> +	(unspec:V [(match_operand:<non_vec> 1 "general_operand"               "")
>>> +		   (match_operand:SI        2 "shift_count_or_setmem_operand" "")
>>
>> This is probably only cosmetic, but should we use nonmemory_operand here
>> instead of shift_count_or_setmem_operand (just like everywhere else now)?
>>
>>> +(define_expand "vec_extract<mode>"
>>> +  [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "")
>>> +	(unspec:<non_vec> [(match_operand:V  1 "register_operand" "")
>>> +			   (match_operand:SI 2 "shift_count_or_setmem_operand" "")]
>>
>> Likewise.
> 
> I just noticed that there are two more UNSPEC_VEC_SET expanders
> in vx-builtins.md.  I guess those should be likewise changed:
> 
> (define_expand "vec_insert<mode>"
>   [(set (match_operand:V_HW                    0 "register_operand" "")
>         (unspec:V_HW [(match_operand:<non_vec> 2 "register_operand" "")
>                       (match_operand:SI        3 "shift_count_or_setmem_operand" "")
>                       (match_operand:V_HW      1 "register_operand" "")]
>                      UNSPEC_VEC_SET))]
>   "TARGET_VX"
>   "")
> 
> (define_expand "vec_promote<mode>"
>   [(set (match_operand:V_HW                    0 "register_operand" "")
>         (unspec:V_HW [(match_operand:<non_vec> 1 "register_operand" "")
>                       (match_operand:SI        2 "shift_count_or_setmem_operand" "")
>                       (match_dup 0)]
>                      UNSPEC_VEC_SET))]
>   "TARGET_VX"
>   "")
> 
> Then the only remaining users of shift_count_or_setmem_operand are the
> actual setmem patterns (so maybe the predicate can be renamed to
> "setmem_operand") :-)

Yes. We probably should also try to get rid of s390_decompose_shift_count. Perhaps it can be merged
into decompose_address as a special case?! At least it should get a new name as well. I'll move
these changes into the next development cycle. I've caused enough stage4 breakage for today ;)

Thanks for reviewing the patches!

Bye,

-Andreas-

[PATCH] S/390: Rename shift_count_or_setmem_operand to setmem_operand

[Andreas Krebbel]

The shift_count_or_setmem_operand predicate is now only used for
setmem patterns anymore.  Rename it together with the related
functions.

2016-03-08  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/constraints.md: Adjust comment.
	("Y"): Adjust comment.  Rename s390_decompose_shift_count to
	s390_decompose_addrstyle_without_index.
	* config/s390/predicates.md (shift_count_or_setmem_operand):
	Rename to setmem_operand.
	* config/s390/s390-protos.h
	(s390_decompose_shift_count): Rename to
	s390_decompose_addrstyle_without_index.
	* config/s390/s390.c (s390_decompose_shift_count)
	(s390_mem_constraint, print_shift_count_operand)
	(print_operand_address, print_operand): Rename
	s390_decompose_shift_count to
	s390_decompose_addrstyle_without_index and rename
	print_shift_count_operand to print_addrstyle_operand troughout the
	file.
	* config/s390/s390.md ("setmem_long_<P:mode>", "*setmem_long")
	("*setmem_long_and", "*setmem_long_31z", "*setmem_long_and_31z"):
	Rename shift_count_or_setmem_operand to setmem_operand.
	* config/s390/vx-builtins.md ("vec_insert<mode>")
	("vec_promote<mode>"): Replace shift_count_or_setmem_operand with
	nonmemory_operand.
---
 gcc/config/s390/constraints.md | 10 +++++-----
 gcc/config/s390/predicates.md  |  4 ++--
 gcc/config/s390/s390-protos.h  |  3 ++-
 gcc/config/s390/s390.c         | 22 +++++++++++++---------
 gcc/config/s390/s390.md        | 12 ++++++------
 gcc/config/s390/vx-builtins.md |  4 ++--
 6 files changed, 30 insertions(+), 25 deletions(-)

diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md
index 60a7edf..7857700 100644
--- a/gcc/config/s390/constraints.md
+++ b/gcc/config/s390/constraints.md
@@ -79,7 +79,7 @@
 ;;         does *not* refer to a literal pool entry.
 ;;    U -- Pointer with short displacement. (deprecated - use ZQZR)
 ;;    W -- Pointer with long displacement. (deprecated - use ZSZT)
-;;    Y -- Shift count operand.
+;;    Y -- Address style operand without index.
 ;;    ZQ -- Pointer without index register and with short displacement.
 ;;    ZR -- Pointer with index register and short displacement.
 ;;    ZS -- Pointer without index register but with long displacement.
@@ -189,12 +189,12 @@
 
 
 (define_address_constraint "Y"
-  "Shift count operand"
+  "Address style operand without index register"
 
-;; Simply check for the basic form of a shift count.  Reload will
-;; take care of making sure we have a proper base register.
+;; Simply check for base + offset style operands.  Reload will take
+;; care of making sure we have a proper base register.
 
-  (match_test "s390_decompose_shift_count (op, NULL, NULL)"  ))
+  (match_test "s390_decompose_addrstyle_without_index (op, NULL, NULL)"  ))
 
 
 ;;    N -- Multiple letter constraint followed by 4 parameter letters.
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index fefefb3..e66f4a4 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -87,7 +87,7 @@
 
 ;; Return true if OP is a valid operand as scalar shift count or setmem.
 
-(define_predicate "shift_count_or_setmem_operand"
+(define_predicate "setmem_operand"
   (match_code "reg, subreg, plus, const_int")
 {
   HOST_WIDE_INT offset;
@@ -98,7 +98,7 @@
     return false;
 
   /* Extract base register and offset.  */
-  if (!s390_decompose_shift_count (op, &base, &offset))
+  if (!s390_decompose_addrstyle_without_index (op, &base, &offset))
     return false;
 
   /* Don't allow any non-base hard registers.  Doing so without
diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 792eaa7..2ccf0bb 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -139,7 +139,8 @@ extern rtx_insn *s390_load_got (void);
 extern rtx s390_get_thread_pointer (void);
 extern void s390_emit_tpf_eh_return (rtx);
 extern bool s390_legitimate_address_without_index_p (rtx);
-extern bool s390_decompose_shift_count (rtx, rtx *, HOST_WIDE_INT *);
+extern bool s390_decompose_addrstyle_without_index (rtx, rtx *,
+						    HOST_WIDE_INT *);
 extern int s390_branch_condition_mask (rtx);
 extern int s390_compare_and_branch_condition_mask (rtx);
 extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT);
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 8924367..4f219be 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2982,13 +2982,16 @@ s390_decompose_address (rtx addr, struct s390_address *out)
   return true;
 }
 
-/* Decompose a RTL expression OP for a shift count into its components,
-   and return the base register in BASE and the offset in OFFSET.
+/* Decompose a RTL expression OP for an address style operand into its
+   components, and return the base register in BASE and the offset in
+   OFFSET.  While OP looks like an address it is never supposed to be
+   used as such.
 
-   Return true if OP is a valid shift count, false if not.  */
+   Return true if OP is a valid address operand, false if not.  */
 
 bool
-s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
+s390_decompose_addrstyle_without_index (rtx op, rtx *base,
+					HOST_WIDE_INT *offset)
 {
   rtx off = NULL_RTX;
 
@@ -3203,7 +3206,7 @@ s390_mem_constraint (const char *str, rtx op)
     case 'Y':
       /* Simply check for the basic form of a shift count.  Reload will
 	 take care of making sure we have a proper base register.  */
-      if (!s390_decompose_shift_count (op, NULL, NULL))
+      if (!s390_decompose_addrstyle_without_index (op, NULL, NULL))
 	return 0;
       break;
     case 'Z':
@@ -6878,13 +6881,13 @@ s390_delegitimize_address (rtx orig_x)
    instead the rightmost bits are interpreted as the value.  */
 
 static void
-print_shift_count_operand (FILE *file, rtx op)
+print_addrstyle_operand (FILE *file, rtx op)
 {
   HOST_WIDE_INT offset;
   rtx base;
 
   /* Extract base register and offset.  */
-  if (!s390_decompose_shift_count (op, &base, &offset))
+  if (!s390_decompose_addrstyle_without_index (op, &base, &offset))
     gcc_unreachable ();
 
   /* Sanity check.  */
@@ -7180,7 +7183,8 @@ print_operand_address (FILE *file, rtx addr)
     'O': print only the displacement of a memory reference or address.
     'R': print only the base register of a memory reference or address.
     'S': print S-type memory reference (base+displacement).
-    'Y': print shift count operand.
+    'Y': print address style operand without index (e.g. shift count or setmem
+	 operand).
 
     'b': print integer X as if it's an unsigned byte.
     'c': print integer X as if it's an signed byte.
@@ -7348,7 +7352,7 @@ print_operand (FILE *file, rtx x, int code)
       break;
 
     case 'Y':
-      print_shift_count_operand (file, x);
+      print_addrstyle_operand (file, x);
       return;
     }
 
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index ca58c42..99974f9 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3296,7 +3296,7 @@
   [(parallel
     [(clobber (match_dup 1))
      (set (match_operand:BLK 0 "memory_operand" "")
-	  (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "")
+	  (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
 		      (match_dup 4)] UNSPEC_REPLICATE_BYTE))
      (use (match_dup 3))
      (clobber (reg:CC CC_REGNUM))])]
@@ -3326,7 +3326,7 @@
 (define_insn "*setmem_long"
   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
-        (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y")
+        (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
 		     (subreg:P (match_dup 3) <modesize>)]
 		     UNSPEC_REPLICATE_BYTE))
    (use (match_operand:<DBL> 1 "register_operand" "d"))
@@ -3340,7 +3340,7 @@
   [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
    (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
         (unspec:BLK [(and:P
-		      (match_operand:P 2 "shift_count_or_setmem_operand" "Y")
+		      (match_operand:P 2 "setmem_operand" "Y")
 		      (match_operand:P 4 "const_int_operand"             "n"))
 		    (subreg:P (match_dup 3) <modesize>)]
 		    UNSPEC_REPLICATE_BYTE))
@@ -3358,7 +3358,7 @@
 (define_insn "*setmem_long_31z"
   [(clobber (match_operand:TI 0 "register_operand" "=d"))
    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
-        (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
+        (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
 		     (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
    (use (match_operand:TI 1 "register_operand" "d"))
    (clobber (reg:CC CC_REGNUM))]
@@ -3371,8 +3371,8 @@
   [(clobber (match_operand:TI 0 "register_operand" "=d"))
    (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
         (unspec:BLK [(and:SI
-		      (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
-		      (match_operand:SI 4 "const_int_operand"             "n"))
+		      (match_operand:SI 2 "setmem_operand" "Y")
+		      (match_operand:SI 4 "const_int_operand" "n"))
 		    (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
    (use (match_operand:TI 1 "register_operand" "d"))
    (clobber (reg:CC CC_REGNUM))]
diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 489bbee..c4a837b 100644
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -150,7 +150,7 @@
 (define_expand "vec_insert<mode>"
   [(set (match_operand:V_HW                    0 "register_operand" "")
 	(unspec:V_HW [(match_operand:<non_vec> 2 "register_operand" "")
-		      (match_operand:SI        3 "shift_count_or_setmem_operand" "")
+		      (match_operand:SI        3 "nonmemory_operand" "")
 		      (match_operand:V_HW      1 "register_operand" "")]
 		     UNSPEC_VEC_SET))]
   "TARGET_VX"
@@ -160,7 +160,7 @@
 (define_expand "vec_promote<mode>"
   [(set (match_operand:V_HW                    0 "register_operand" "")
 	(unspec:V_HW [(match_operand:<non_vec> 1 "register_operand" "")
-		      (match_operand:SI        2 "shift_count_or_setmem_operand" "")
+		      (match_operand:SI        2 "nonmemory_operand" "")
 		      (match_dup 0)]
 		     UNSPEC_VEC_SET))]
   "TARGET_VX"
-- 
1.9.1