From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 55444 invoked by alias); 10 Mar 2016 16:37:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 55378 invoked by uid 89); 10 Mar 2016 16:37:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=*movtf_aarch64, postpone X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 10 Mar 2016 16:37:40 +0000 Received: from arm.com (e107456-lin.cambridge.arm.com [10.2.206.78]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id u2AGbaRF026855; Thu, 10 Mar 2016 16:37:36 GMT Date: Thu, 10 Mar 2016 16:37:00 -0000 From: James Greenhalgh To: Evandro Menezes Cc: Wilco Dijkstra , "gcc-patches@gcc.gnu.org" , nd , Marcus Shawcroft , Kyrylo Tkachov , richard.earnshaw@arm.com Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register Message-ID: <20160310163736.GA8272@arm.com> References: <56D0D50E.8030802@samsung.com> <56D4D02C.6030309@samsung.com> <56D5E8B6.1090900@samsung.com> <56E0972F.3060207@samsung.com> <20160310132327.GA38844@arm.com> <56E1A061.5080901@samsung.com> <56E1A18F.5000006@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <56E1A18F.5000006@samsung.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2016-03/txt/msg00648.txt.bz2 On Thu, Mar 10, 2016 at 10:32:15AM -0600, Evandro Menezes wrote: > >I agree to postpone until GCC 7. > > > > [AArch64] Replace insn to zero up SIMD registers > > > > gcc/ > > * config/aarch64/aarch64.md > > (*movhf_aarch64): Add "movi %0, #0" to zero up register. > > (*movsf_aarch64): Likewise and add "simd" attributes. > > (*movdf_aarch64): Likewise. > > > >This patch removes the FP attributes from the HF, SF, DF, TF moves. > > And now, with the patch. :-/ > Thanks for sticking with it. This is OK for GCC 7 when development opens. Remember to mention the most recent changes in your Changelog entry (Remove "fp" attribute from *movhf_aarch64 and *movtf_aarch64). Thanks, James