* [PATCH] Improve other 13 define_insns
@ 2016-05-04 19:43 Jakub Jelinek
2016-05-06 11:47 ` Kirill Yukhin
2016-05-12 14:22 ` Kirill Yukhin
0 siblings, 2 replies; 6+ messages in thread
From: Jakub Jelinek @ 2016-05-04 19:43 UTC (permalink / raw)
To: Uros Bizjak, Kirill Yukhin; +Cc: gcc-patches
Hi!
This patch tweaks more define_insns at once, again all the insns
should be already in AVX512F or AVX512VL.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2016-05-04 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (sse_shufps_<mode>, sse_storehps, sse_loadhps,
sse_storelps, sse_movss, avx2_vec_dup<mode>, avx2_vec_dupv8sf_1,
sse2_shufpd_<mode>, sse2_storehpd, sse2_storelpd, sse2_loadhpd,
sse2_loadlpd, sse2_movsd): Use v instead of x in vex or maybe_vex
alternatives, use maybe_evex instead of vex in prefix.
--- gcc/config/i386/sse.md.jj 2016-05-04 14:36:08.000000000 +0200
+++ gcc/config/i386/sse.md 2016-05-04 15:16:44.180894303 +0200
@@ -6219,11 +6219,11 @@ (define_insn "sse_shufps_v4sf_mask"
(set_attr "mode" "V4SF")])
(define_insn "sse_shufps_<mode>"
- [(set (match_operand:VI4F_128 0 "register_operand" "=x,x")
+ [(set (match_operand:VI4F_128 0 "register_operand" "=x,v")
(vec_select:VI4F_128
(vec_concat:<ssedoublevecmode>
- (match_operand:VI4F_128 1 "register_operand" "0,x")
- (match_operand:VI4F_128 2 "vector_operand" "xBm,xm"))
+ (match_operand:VI4F_128 1 "register_operand" "0,v")
+ (match_operand:VI4F_128 2 "vector_operand" "xBm,vm"))
(parallel [(match_operand 3 "const_0_to_3_operand")
(match_operand 4 "const_0_to_3_operand")
(match_operand 5 "const_4_to_7_operand")
@@ -6250,13 +6250,13 @@ (define_insn "sse_shufps_<mode>"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseshuf")
(set_attr "length_immediate" "1")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "V4SF")])
(define_insn "sse_storehps"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,v,v")
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" "x,x,o")
+ (match_operand:V4SF 1 "nonimmediate_operand" "v,v,o")
(parallel [(const_int 2) (const_int 3)])))]
"TARGET_SSE"
"@
@@ -6288,12 +6288,12 @@ (define_expand "sse_loadhps_exp"
})
(define_insn "sse_loadhps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,o")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,v,x,v,o")
(vec_concat:V4SF
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" " 0,x,0,x,0")
+ (match_operand:V4SF 1 "nonimmediate_operand" " 0,v,0,v,0")
(parallel [(const_int 0) (const_int 1)]))
- (match_operand:V2SF 2 "nonimmediate_operand" " m,m,x,x,x")))]
+ (match_operand:V2SF 2 "nonimmediate_operand" " m,m,x,v,v")))]
"TARGET_SSE"
"@
movhps\t{%2, %0|%0, %q2}
@@ -6303,13 +6303,13 @@ (define_insn "sse_loadhps"
%vmovlps\t{%2, %H0|%H0, %2}"
[(set_attr "isa" "noavx,avx,noavx,avx,*")
(set_attr "type" "ssemov")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
+ (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex")
(set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")])
(define_insn "sse_storelps"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,v,v")
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" " x,x,m")
+ (match_operand:V4SF 1 "nonimmediate_operand" " v,v,m")
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"@
@@ -6341,11 +6341,11 @@ (define_expand "sse_loadlps_exp"
})
(define_insn "sse_loadlps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,m")
+ [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,v,x,v,m")
(vec_concat:V4SF
- (match_operand:V2SF 2 "nonimmediate_operand" " 0,x,m,m,x")
+ (match_operand:V2SF 2 "nonimmediate_operand" " 0,v,m,m,v")
(vec_select:V2SF
- (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0,x,0")
+ (match_operand:V4SF 1 "nonimmediate_operand" " x,v,0,v,0")
(parallel [(const_int 2) (const_int 3)]))))]
"TARGET_SSE"
"@
@@ -6357,14 +6357,14 @@ (define_insn "sse_loadlps"
[(set_attr "isa" "noavx,avx,noavx,avx,*")
(set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov")
(set_attr "length_immediate" "1,1,*,*,*")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
+ (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex")
(set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
(define_insn "sse_movss"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
+ [(set (match_operand:V4SF 0 "register_operand" "=x,v")
(vec_merge:V4SF
- (match_operand:V4SF 2 "register_operand" " x,x")
- (match_operand:V4SF 1 "register_operand" " 0,x")
+ (match_operand:V4SF 2 "register_operand" " x,v")
+ (match_operand:V4SF 1 "register_operand" " 0,v")
(const_int 1)))]
"TARGET_SSE"
"@
@@ -6372,31 +6372,31 @@ (define_insn "sse_movss"
vmovss\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "ssemov")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "SF")])
(define_insn "avx2_vec_dup<mode>"
- [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
+ [(set (match_operand:VF1_128_256 0 "register_operand" "=v")
(vec_duplicate:VF1_128_256
(vec_select:SF
- (match_operand:V4SF 1 "register_operand" "x")
+ (match_operand:V4SF 1 "register_operand" "v")
(parallel [(const_int 0)]))))]
"TARGET_AVX2"
"vbroadcastss\t{%1, %0|%0, %1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "<MODE>")])
(define_insn "avx2_vec_dupv8sf_1"
- [(set (match_operand:V8SF 0 "register_operand" "=x")
+ [(set (match_operand:V8SF 0 "register_operand" "=v")
(vec_duplicate:V8SF
(vec_select:SF
- (match_operand:V8SF 1 "register_operand" "x")
+ (match_operand:V8SF 1 "register_operand" "v")
(parallel [(const_int 0)]))))]
"TARGET_AVX2"
"vbroadcastss\t{%x1, %0|%0, %x1}"
[(set_attr "type" "sselog1")
- (set_attr "prefix" "vex")
+ (set_attr "prefix" "maybe_evex")
(set_attr "mode" "V8SF")])
(define_insn "avx512f_vec_dup<mode>_1"
@@ -8248,11 +8262,11 @@ (define_insn "vec_interleave_lowv2di<mas
(set_attr "mode" "TI")])
(define_insn "sse2_shufpd_<mode>"
- [(set (match_operand:VI8F_128 0 "register_operand" "=x,x")
+ [(set (match_operand:VI8F_128 0 "register_operand" "=x,v")
(vec_select:VI8F_128
(vec_concat:<ssedoublevecmode>
- (match_operand:VI8F_128 1 "register_operand" "0,x")
- (match_operand:VI8F_128 2 "vector_operand" "xBm,xm"))
+ (match_operand:VI8F_128 1 "register_operand" "0,v")
+ (match_operand:VI8F_128 2 "vector_operand" "xBm,vm"))
(parallel [(match_operand 3 "const_0_to_1_operand")
(match_operand 4 "const_2_to_3_operand")])))]
"TARGET_SSE2"
@@ -8275,15 +8289,15 @@ (define_insn "sse2_shufpd_<mode>"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseshuf")
(set_attr "length_immediate" "1")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "V2DF")])
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "sse2_storehpd"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,x,*f,r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" " x,0,x,o,o,o")
+ (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
(parallel [(const_int 1)])))]
"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
@@ -8301,7 +8315,7 @@ (define_insn "sse2_storehpd"
(not (match_test "TARGET_AVX")))
(const_string "1")
(const_string "*")))
- (set_attr "prefix" "maybe_vex,orig,vex,*,*,*")
+ (set_attr "prefix" "maybe_vex,orig,maybe_evex,*,*,*")
(set_attr "mode" "V1DF,V1DF,V2DF,DF,DF,DF")])
(define_split
@@ -8346,7 +8346,7 @@
(define_insn "sse2_storelpd"
[(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" " x,x,m,m,m")
+ (match_operand:V2DF 1 "nonimmediate_operand" " v,x,m,m,m")
(parallel [(const_int 0)])))]
"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
@@ -8393,14 +8407,14 @@ (define_expand "sse2_loadhpd_exp"
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "sse2_loadhpd"
[(set (match_operand:V2DF 0 "nonimmediate_operand"
- "=x,x,x,x,o,o ,o")
+ "=x,v,x,v,o,o ,o")
(vec_concat:V2DF
(vec_select:DF
(match_operand:V2DF 1 "nonimmediate_operand"
- " 0,x,0,x,0,0 ,0")
+ " 0,v,0,v,0,0 ,0")
(parallel [(const_int 0)]))
(match_operand:DF 2 "nonimmediate_operand"
- " m,m,x,x,x,*f,r")))]
+ " m,m,x,v,x,*f,r")))]
"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
movhpd\t{%2, %0|%0, %2}
@@ -8413,7 +8427,7 @@ (define_insn "sse2_loadhpd"
[(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")
(set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov")
(set_attr "prefix_data16" "1,*,*,*,*,*,*")
- (set_attr "prefix" "orig,vex,orig,vex,*,*,*")
+ (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,*,*,*")
(set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])
(define_split
@@ -8449,13 +8463,13 @@ (define_expand "sse2_loadlpd_exp"
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "sse2_loadlpd"
[(set (match_operand:V2DF 0 "nonimmediate_operand"
- "=x,x,x,x,x,x,x,x,m,m ,m")
+ "=v,x,v,x,v,x,x,v,m,m ,m")
(vec_concat:V2DF
(match_operand:DF 2 "nonimmediate_operand"
- "xm,m,m,x,x,0,0,x,x,*f,r")
+ "vm,m,m,x,v,0,0,v,x,*f,r")
(vec_select:DF
(match_operand:V2DF 1 "vector_move_operand"
- " C,0,x,0,x,x,o,o,0,0 ,0")
+ " C,0,v,0,v,x,o,o,0,0 ,0")
(parallel [(const_int 1)]))))]
"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
@@ -8482,7 +8496,7 @@ (define_insn "sse2_loadlpd"
(const_string "ssemov")))
(set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*")
(set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*")
- (set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*")
+ (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex,orig,orig,maybe_evex,*,*,*")
(set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,DF,DF,DF")])
(define_split
@@ -8495,10 +8509,10 @@ (define_split
"operands[0] = adjust_address (operands[0], DFmode, 0);")
(define_insn "sse2_movsd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,x,x,x,o")
+ [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,x,v,m,x,x,v,o")
(vec_merge:V2DF
- (match_operand:V2DF 2 "nonimmediate_operand" " x,x,m,m,x,0,0,x,0")
- (match_operand:V2DF 1 "nonimmediate_operand" " 0,x,0,x,0,x,o,o,x")
+ (match_operand:V2DF 2 "nonimmediate_operand" " x,v,m,m,v,0,0,v,0")
+ (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,0,v,0,x,o,o,v")
(const_int 1)))]
"TARGET_SSE2"
"@
@@ -8524,7 +8538,7 @@ (define_insn "sse2_movsd"
(const_string "1")
(const_string "*")))
(set_attr "length_immediate" "*,*,*,*,*,1,*,*,*")
- (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex")
+ (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex,orig,orig,maybe_evex,maybe_vex")
(set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
(define_insn "vec_dupv2df<mask_name>"
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Improve other 13 define_insns
2016-05-04 19:43 [PATCH] Improve other 13 define_insns Jakub Jelinek
@ 2016-05-06 11:47 ` Kirill Yukhin
2016-05-12 14:22 ` Kirill Yukhin
1 sibling, 0 replies; 6+ messages in thread
From: Kirill Yukhin @ 2016-05-06 11:47 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, gcc-patches
On 04 May 21:43, Jakub Jelinek wrote:
> Hi!
>
> This patch tweaks more define_insns at once, again all the insns
> should be already in AVX512F or AVX512VL.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
OK for trunk.
--
Thanks, K
>
> 2016-05-04 Jakub Jelinek <jakub@redhat.com>
>
> * config/i386/sse.md (sse_shufps_<mode>, sse_storehps, sse_loadhps,
> sse_storelps, sse_movss, avx2_vec_dup<mode>, avx2_vec_dupv8sf_1,
> sse2_shufpd_<mode>, sse2_storehpd, sse2_storelpd, sse2_loadhpd,
> sse2_loadlpd, sse2_movsd): Use v instead of x in vex or maybe_vex
> alternatives, use maybe_evex instead of vex in prefix.
>
> --- gcc/config/i386/sse.md.jj 2016-05-04 14:36:08.000000000 +0200
> +++ gcc/config/i386/sse.md 2016-05-04 15:16:44.180894303 +0200
> @@ -6219,11 +6219,11 @@ (define_insn "sse_shufps_v4sf_mask"
> (set_attr "mode" "V4SF")])
>
> (define_insn "sse_shufps_<mode>"
> - [(set (match_operand:VI4F_128 0 "register_operand" "=x,x")
> + [(set (match_operand:VI4F_128 0 "register_operand" "=x,v")
> (vec_select:VI4F_128
> (vec_concat:<ssedoublevecmode>
> - (match_operand:VI4F_128 1 "register_operand" "0,x")
> - (match_operand:VI4F_128 2 "vector_operand" "xBm,xm"))
> + (match_operand:VI4F_128 1 "register_operand" "0,v")
> + (match_operand:VI4F_128 2 "vector_operand" "xBm,vm"))
> (parallel [(match_operand 3 "const_0_to_3_operand")
> (match_operand 4 "const_0_to_3_operand")
> (match_operand 5 "const_4_to_7_operand")
> @@ -6250,13 +6250,13 @@ (define_insn "sse_shufps_<mode>"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseshuf")
> (set_attr "length_immediate" "1")
> - (set_attr "prefix" "orig,vex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "V4SF")])
>
> (define_insn "sse_storehps"
> - [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
> + [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,v,v")
> (vec_select:V2SF
> - (match_operand:V4SF 1 "nonimmediate_operand" "x,x,o")
> + (match_operand:V4SF 1 "nonimmediate_operand" "v,v,o")
> (parallel [(const_int 2) (const_int 3)])))]
> "TARGET_SSE"
> "@
> @@ -6288,12 +6288,12 @@ (define_expand "sse_loadhps_exp"
> })
>
> (define_insn "sse_loadhps"
> - [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,o")
> + [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,v,x,v,o")
> (vec_concat:V4SF
> (vec_select:V2SF
> - (match_operand:V4SF 1 "nonimmediate_operand" " 0,x,0,x,0")
> + (match_operand:V4SF 1 "nonimmediate_operand" " 0,v,0,v,0")
> (parallel [(const_int 0) (const_int 1)]))
> - (match_operand:V2SF 2 "nonimmediate_operand" " m,m,x,x,x")))]
> + (match_operand:V2SF 2 "nonimmediate_operand" " m,m,x,v,v")))]
> "TARGET_SSE"
> "@
> movhps\t{%2, %0|%0, %q2}
> @@ -6303,13 +6303,13 @@ (define_insn "sse_loadhps"
> %vmovlps\t{%2, %H0|%H0, %2}"
> [(set_attr "isa" "noavx,avx,noavx,avx,*")
> (set_attr "type" "ssemov")
> - (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
> + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex")
> (set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")])
>
> (define_insn "sse_storelps"
> - [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
> + [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,v,v")
> (vec_select:V2SF
> - (match_operand:V4SF 1 "nonimmediate_operand" " x,x,m")
> + (match_operand:V4SF 1 "nonimmediate_operand" " v,v,m")
> (parallel [(const_int 0) (const_int 1)])))]
> "TARGET_SSE"
> "@
> @@ -6341,11 +6341,11 @@ (define_expand "sse_loadlps_exp"
> })
>
> (define_insn "sse_loadlps"
> - [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,m")
> + [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,v,x,v,m")
> (vec_concat:V4SF
> - (match_operand:V2SF 2 "nonimmediate_operand" " 0,x,m,m,x")
> + (match_operand:V2SF 2 "nonimmediate_operand" " 0,v,m,m,v")
> (vec_select:V2SF
> - (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0,x,0")
> + (match_operand:V4SF 1 "nonimmediate_operand" " x,v,0,v,0")
> (parallel [(const_int 2) (const_int 3)]))))]
> "TARGET_SSE"
> "@
> @@ -6357,14 +6357,14 @@ (define_insn "sse_loadlps"
> [(set_attr "isa" "noavx,avx,noavx,avx,*")
> (set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov")
> (set_attr "length_immediate" "1,1,*,*,*")
> - (set_attr "prefix" "orig,vex,orig,vex,maybe_vex")
> + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex")
> (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")])
>
> (define_insn "sse_movss"
> - [(set (match_operand:V4SF 0 "register_operand" "=x,x")
> + [(set (match_operand:V4SF 0 "register_operand" "=x,v")
> (vec_merge:V4SF
> - (match_operand:V4SF 2 "register_operand" " x,x")
> - (match_operand:V4SF 1 "register_operand" " 0,x")
> + (match_operand:V4SF 2 "register_operand" " x,v")
> + (match_operand:V4SF 1 "register_operand" " 0,v")
> (const_int 1)))]
> "TARGET_SSE"
> "@
> @@ -6372,31 +6372,31 @@ (define_insn "sse_movss"
> vmovss\t{%2, %1, %0|%0, %1, %2}"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "ssemov")
> - (set_attr "prefix" "orig,vex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "SF")])
>
> (define_insn "avx2_vec_dup<mode>"
> - [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
> + [(set (match_operand:VF1_128_256 0 "register_operand" "=v")
> (vec_duplicate:VF1_128_256
> (vec_select:SF
> - (match_operand:V4SF 1 "register_operand" "x")
> + (match_operand:V4SF 1 "register_operand" "v")
> (parallel [(const_int 0)]))))]
> "TARGET_AVX2"
> "vbroadcastss\t{%1, %0|%0, %1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix" "vex")
> + (set_attr "prefix" "maybe_evex")
> (set_attr "mode" "<MODE>")])
>
> (define_insn "avx2_vec_dupv8sf_1"
> - [(set (match_operand:V8SF 0 "register_operand" "=x")
> + [(set (match_operand:V8SF 0 "register_operand" "=v")
> (vec_duplicate:V8SF
> (vec_select:SF
> - (match_operand:V8SF 1 "register_operand" "x")
> + (match_operand:V8SF 1 "register_operand" "v")
> (parallel [(const_int 0)]))))]
> "TARGET_AVX2"
> "vbroadcastss\t{%x1, %0|%0, %x1}"
> [(set_attr "type" "sselog1")
> - (set_attr "prefix" "vex")
> + (set_attr "prefix" "maybe_evex")
> (set_attr "mode" "V8SF")])
>
> (define_insn "avx512f_vec_dup<mode>_1"
> @@ -8248,11 +8262,11 @@ (define_insn "vec_interleave_lowv2di<mas
> (set_attr "mode" "TI")])
>
> (define_insn "sse2_shufpd_<mode>"
> - [(set (match_operand:VI8F_128 0 "register_operand" "=x,x")
> + [(set (match_operand:VI8F_128 0 "register_operand" "=x,v")
> (vec_select:VI8F_128
> (vec_concat:<ssedoublevecmode>
> - (match_operand:VI8F_128 1 "register_operand" "0,x")
> - (match_operand:VI8F_128 2 "vector_operand" "xBm,xm"))
> + (match_operand:VI8F_128 1 "register_operand" "0,v")
> + (match_operand:VI8F_128 2 "vector_operand" "xBm,vm"))
> (parallel [(match_operand 3 "const_0_to_1_operand")
> (match_operand 4 "const_2_to_3_operand")])))]
> "TARGET_SSE2"
> @@ -8275,15 +8289,15 @@ (define_insn "sse2_shufpd_<mode>"
> [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseshuf")
> (set_attr "length_immediate" "1")
> - (set_attr "prefix" "orig,vex")
> + (set_attr "prefix" "orig,maybe_evex")
> (set_attr "mode" "V2DF")])
>
> ;; Avoid combining registers from different units in a single alternative,
> ;; see comment above inline_secondary_memory_needed function in i386.c
> (define_insn "sse2_storehpd"
> - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,x,*f,r")
> + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
> (vec_select:DF
> - (match_operand:V2DF 1 "nonimmediate_operand" " x,0,x,o,o,o")
> + (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
> (parallel [(const_int 1)])))]
> "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
> "@
> @@ -8301,7 +8315,7 @@ (define_insn "sse2_storehpd"
> (not (match_test "TARGET_AVX")))
> (const_string "1")
> (const_string "*")))
> - (set_attr "prefix" "maybe_vex,orig,vex,*,*,*")
> + (set_attr "prefix" "maybe_vex,orig,maybe_evex,*,*,*")
> (set_attr "mode" "V1DF,V1DF,V2DF,DF,DF,DF")])
>
> (define_split
> @@ -8346,7 +8346,7 @@
> (define_insn "sse2_storelpd"
> [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
> (vec_select:DF
> - (match_operand:V2DF 1 "nonimmediate_operand" " x,x,m,m,m")
> + (match_operand:V2DF 1 "nonimmediate_operand" " v,x,m,m,m")
> (parallel [(const_int 0)])))]
> "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
> "@
> @@ -8393,14 +8407,14 @@ (define_expand "sse2_loadhpd_exp"
> ;; see comment above inline_secondary_memory_needed function in i386.c
> (define_insn "sse2_loadhpd"
> [(set (match_operand:V2DF 0 "nonimmediate_operand"
> - "=x,x,x,x,o,o ,o")
> + "=x,v,x,v,o,o ,o")
> (vec_concat:V2DF
> (vec_select:DF
> (match_operand:V2DF 1 "nonimmediate_operand"
> - " 0,x,0,x,0,0 ,0")
> + " 0,v,0,v,0,0 ,0")
> (parallel [(const_int 0)]))
> (match_operand:DF 2 "nonimmediate_operand"
> - " m,m,x,x,x,*f,r")))]
> + " m,m,x,v,x,*f,r")))]
> "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> movhpd\t{%2, %0|%0, %2}
> @@ -8413,7 +8427,7 @@ (define_insn "sse2_loadhpd"
> [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*")
> (set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov")
> (set_attr "prefix_data16" "1,*,*,*,*,*,*")
> - (set_attr "prefix" "orig,vex,orig,vex,*,*,*")
> + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,*,*,*")
> (set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")])
>
> (define_split
> @@ -8449,13 +8463,13 @@ (define_expand "sse2_loadlpd_exp"
> ;; see comment above inline_secondary_memory_needed function in i386.c
> (define_insn "sse2_loadlpd"
> [(set (match_operand:V2DF 0 "nonimmediate_operand"
> - "=x,x,x,x,x,x,x,x,m,m ,m")
> + "=v,x,v,x,v,x,x,v,m,m ,m")
> (vec_concat:V2DF
> (match_operand:DF 2 "nonimmediate_operand"
> - "xm,m,m,x,x,0,0,x,x,*f,r")
> + "vm,m,m,x,v,0,0,v,x,*f,r")
> (vec_select:DF
> (match_operand:V2DF 1 "vector_move_operand"
> - " C,0,x,0,x,x,o,o,0,0 ,0")
> + " C,0,v,0,v,x,o,o,0,0 ,0")
> (parallel [(const_int 1)]))))]
> "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
> "@
> @@ -8482,7 +8496,7 @@ (define_insn "sse2_loadlpd"
> (const_string "ssemov")))
> (set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*")
> (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*")
> - (set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*")
> + (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex,orig,orig,maybe_evex,*,*,*")
> (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,DF,DF,DF")])
>
> (define_split
> @@ -8495,10 +8509,10 @@ (define_split
> "operands[0] = adjust_address (operands[0], DFmode, 0);")
>
> (define_insn "sse2_movsd"
> - [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,x,x,x,o")
> + [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,x,v,m,x,x,v,o")
> (vec_merge:V2DF
> - (match_operand:V2DF 2 "nonimmediate_operand" " x,x,m,m,x,0,0,x,0")
> - (match_operand:V2DF 1 "nonimmediate_operand" " 0,x,0,x,0,x,o,o,x")
> + (match_operand:V2DF 2 "nonimmediate_operand" " x,v,m,m,v,0,0,v,0")
> + (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,0,v,0,x,o,o,v")
> (const_int 1)))]
> "TARGET_SSE2"
> "@
> @@ -8524,7 +8538,7 @@ (define_insn "sse2_movsd"
> (const_string "1")
> (const_string "*")))
> (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*")
> - (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex")
> + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex,orig,orig,maybe_evex,maybe_vex")
> (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
>
> (define_insn "vec_dupv2df<mask_name>"
>
> Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Improve other 13 define_insns
2016-05-04 19:43 [PATCH] Improve other 13 define_insns Jakub Jelinek
2016-05-06 11:47 ` Kirill Yukhin
@ 2016-05-12 14:22 ` Kirill Yukhin
2016-05-12 18:42 ` Jakub Jelinek
1 sibling, 1 reply; 6+ messages in thread
From: Kirill Yukhin @ 2016-05-12 14:22 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, gcc-patches
Hi Jakub,
On 04 May 21:43, Jakub Jelinek wrote:
> Hi!
>
> This patch tweaks more define_insns at once, again all the insns
> should be already in AVX512F or AVX512VL.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2016-05-04 Jakub Jelinek <jakub@redhat.com>
>
> * config/i386/sse.md (sse_shufps_<mode>, sse_storehps, sse_loadhps,
> sse_storelps, sse_movss, avx2_vec_dup<mode>, avx2_vec_dupv8sf_1,
> sse2_shufpd_<mode>, sse2_storehpd, sse2_storelpd, sse2_loadhpd,
> sse2_loadlpd, sse2_movsd): Use v instead of x in vex or maybe_vex
> alternatives, use maybe_evex instead of vex in prefix.
>
> ;; Avoid combining registers from different units in a single alternative,
> ;; see comment above inline_secondary_memory_needed function in i386.c
> (define_insn "sse2_storehpd"
> - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,x,*f,r")
> + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
> (vec_select:DF
> - (match_operand:V2DF 1 "nonimmediate_operand" " x,0,x,o,o,o")
> + (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
Same (as [1]) here.
Testing this fix:
@@ -8426,7 +8426,7 @@
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "sse2_storehpd"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,Yv,x,*f,r")
(vec_select:DF
(match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
[1] - https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00908.html
--
Thanks, K
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Improve other 13 define_insns
2016-05-12 14:22 ` Kirill Yukhin
@ 2016-05-12 18:42 ` Jakub Jelinek
2016-05-13 11:47 ` Kirill Yukhin
0 siblings, 1 reply; 6+ messages in thread
From: Jakub Jelinek @ 2016-05-12 18:42 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, gcc-patches
On Thu, May 12, 2016 at 05:20:02PM +0300, Kirill Yukhin wrote:
> > 2016-05-04 Jakub Jelinek <jakub@redhat.com>
> >
> > * config/i386/sse.md (sse_shufps_<mode>, sse_storehps, sse_loadhps,
> > sse_storelps, sse_movss, avx2_vec_dup<mode>, avx2_vec_dupv8sf_1,
> > sse2_shufpd_<mode>, sse2_storehpd, sse2_storelpd, sse2_loadhpd,
> > sse2_loadlpd, sse2_movsd): Use v instead of x in vex or maybe_vex
> > alternatives, use maybe_evex instead of vex in prefix.
> >
> > ;; Avoid combining registers from different units in a single alternative,
> > ;; see comment above inline_secondary_memory_needed function in i386.c
> > (define_insn "sse2_storehpd"
> > - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,x,*f,r")
> > + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
> > (vec_select:DF
> > - (match_operand:V2DF 1 "nonimmediate_operand" " x,0,x,o,o,o")
> > + (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
> Same (as [1]) here.
> Testing this fix:
> @@ -8426,7 +8426,7 @@
> ;; Avoid combining registers from different units in a single alternative,
> ;; see comment above inline_secondary_memory_needed function in i386.c
> (define_insn "sse2_storehpd"
> - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
> + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,Yv,x,*f,r")
> (vec_select:DF
> (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
>
>
Sorry for that, yes, this is needed.
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Improve other 13 define_insns
2016-05-12 18:42 ` Jakub Jelinek
@ 2016-05-13 11:47 ` Kirill Yukhin
2016-05-13 11:51 ` Jakub Jelinek
0 siblings, 1 reply; 6+ messages in thread
From: Kirill Yukhin @ 2016-05-13 11:47 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, gcc-patches
Hello,
On 12 May 20:42, Jakub Jelinek wrote:
> On Thu, May 12, 2016 at 05:20:02PM +0300, Kirill Yukhin wrote:
> > > 2016-05-04 Jakub Jelinek <jakub@redhat.com>
> > >
> > > * config/i386/sse.md (sse_shufps_<mode>, sse_storehps, sse_loadhps,
> > > sse_storelps, sse_movss, avx2_vec_dup<mode>, avx2_vec_dupv8sf_1,
> > > sse2_shufpd_<mode>, sse2_storehpd, sse2_storelpd, sse2_loadhpd,
> > > sse2_loadlpd, sse2_movsd): Use v instead of x in vex or maybe_vex
> > > alternatives, use maybe_evex instead of vex in prefix.
> > >
> > > ;; Avoid combining registers from different units in a single alternative,
> > > ;; see comment above inline_secondary_memory_needed function in i386.c
> > > (define_insn "sse2_storehpd"
> > > - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,x,*f,r")
> > > + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
> > > (vec_select:DF
> > > - (match_operand:V2DF 1 "nonimmediate_operand" " x,0,x,o,o,o")
> > > + (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
> > Same (as [1]) here.
> > Testing this fix:
> > @@ -8426,7 +8426,7 @@
> > ;; Avoid combining registers from different units in a single alternative,
> > ;; see comment above inline_secondary_memory_needed function in i386.c
> > (define_insn "sse2_storehpd"
> > - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
> > + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,Yv,x,*f,r")
> > (vec_select:DF
> > (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
> >
> >
>
> Sorry for that, yes, this is needed.
NP. Below is the patch which fixes both issues.
It also revealed, that for "*and" pattern 32 byte long
internal buffer is not enough.
I've extended bunch of such buffers to 128 bytes.
Probably we might want to re-factor all static char arrays w/
std::string or at least check how many bytes snprintf actually prints
and ICE if overflow.
Bootstrapped & regtested on x86, 32/64b. Will check into main trunk.
gcc/
* gcc/config/i386/sse.md (define_insn "*andnot<mode>3"): Extend static
array to 128 chars.
(define_insn "*andnottf3"): Ditto.
(define_insn "*<code><mode>3"/any_logic): Ditto.
(define_insn "*<code>tf3"/any_logic): Ditto.
(define_insn "*vec_concatv2sf_sse4_1"): Use Yv constraint for scalar
operand to block AVX-512VL insn variant emit when it is not enabled.
(define_insn "sse2_storehpd"): Ditto.
--
Thanks, K
>
> Jakub
commit fa17bc4026602e7bc79fd818ab97c991864c2f7c
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Fri May 13 12:38:50 2016 +0300
AVX-512. Fix constraints for scalar patterns. Extend 32b static buffers.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d77227a..1ece86f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3027,7 +3027,7 @@
(match_operand:MODEF 2 "register_operand" "x,x,v,v")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
{
- static char buf[32];
+ static char buf[128];
const char *ops;
const char *suffix
= (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>";
@@ -3094,7 +3094,7 @@
(match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
"TARGET_SSE"
{
- static char buf[32];
+ static char buf[128];
const char *ops;
const char *tmp
= (which_alternative >= 2 ? "pandnq"
@@ -3150,7 +3150,7 @@
(match_operand:MODEF 2 "register_operand" "x,x,v,v")))]
"SSE_FLOAT_MODE_P (<MODE>mode)"
{
- static char buf[32];
+ static char buf[128];
const char *ops;
const char *suffix
= (get_attr_mode (insn) == MODE_V4SF) ? "ps" : "<ssevecmodesuffix>";
@@ -3225,7 +3225,7 @@
"TARGET_SSE
&& ix86_binary_operator_ok (<CODE>, TFmode, operands)"
{
- static char buf[32];
+ static char buf[128];
const char *ops;
const char *tmp
= (which_alternative >= 2 ? "p<logic>q"
@@ -6546,12 +6546,12 @@
;; unpcklps with register source since it is shorter.
(define_insn "*vec_concatv2sf_sse4_1"
[(set (match_operand:V2SF 0 "register_operand"
- "=Yr,*x,v,Yr,*x,v,v,*y ,*y")
+ "=Yr,*x, v,Yr,*x,v,v,*y ,*y")
(vec_concat:V2SF
(match_operand:SF 1 "nonimmediate_operand"
- " 0, 0,v, 0,0, v,m, 0 , m")
+ " 0, 0,Yv, 0,0, v,m, 0 , m")
(match_operand:SF 2 "vector_move_operand"
- " Yr,*x,v, m,m, m,C,*ym, C")))]
+ " Yr,*x,Yv, m,m, m,C,*ym, C")))]
"TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
unpcklps\t{%2, %0|%0, %2}
@@ -8426,9 +8426,9 @@
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.c
(define_insn "sse2_storehpd"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,Yv,x,*f,r")
(vec_select:DF
- (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o")
+ (match_operand:V2DF 1 "nonimmediate_operand" " v,0, v,o,o,o")
(parallel [(const_int 1)])))]
"TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Improve other 13 define_insns
2016-05-13 11:47 ` Kirill Yukhin
@ 2016-05-13 11:51 ` Jakub Jelinek
0 siblings, 0 replies; 6+ messages in thread
From: Jakub Jelinek @ 2016-05-13 11:51 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, gcc-patches
On Fri, May 13, 2016 at 02:46:36PM +0300, Kirill Yukhin wrote:
> NP. Below is the patch which fixes both issues.
> It also revealed, that for "*and" pattern 32 byte long
> internal buffer is not enough.
> I've extended bunch of such buffers to 128 bytes.
>
> Probably we might want to re-factor all static char arrays w/
> std::string or at least check how many bytes snprintf actually prints
> and ICE if overflow.
I'd prefer not to use std::string for that, but snprintf and asserts
on the result look reasonable thing to do (though, the snprintf shouldn't
be inside of the assert) obviously.
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-05-04 19:43 [PATCH] Improve other 13 define_insns Jakub Jelinek
2016-05-06 11:47 ` Kirill Yukhin
2016-05-12 14:22 ` Kirill Yukhin
2016-05-12 18:42 ` Jakub Jelinek
2016-05-13 11:47 ` Kirill Yukhin
2016-05-13 11:51 ` Jakub Jelinek
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