* [PATCH] Fix up vpmulhrsw for -mavx512vl -mno-avx512bw
@ 2016-05-13 17:17 Jakub Jelinek
2016-05-18 8:51 ` Kirill Yukhin
0 siblings, 1 reply; 2+ messages in thread
From: Jakub Jelinek @ 2016-05-13 17:17 UTC (permalink / raw)
To: Uros Bizjak, Kirill Yukhin; +Cc: gcc-patches
Hi!
vpmulhrsw is AVX512BW & AVX512VL insn, so we shouldn't enable it just
when AVX512VL is on.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
trunk?
2016-05-13 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Use
constraint x instead of v in second alternative, add avx512bw
alternative.
* gcc.target/i386/avx512vl-vpmulhrsw-3.c: New test.
* gcc.target/i386/avx512bw-vpmulhrsw-3.c: New test.
--- gcc/config/i386/sse.md.jj 2016-05-13 14:46:03.563465879 +0200
+++ gcc/config/i386/sse.md 2016-05-13 15:18:24.791195754 +0200
@@ -14158,16 +14158,16 @@ (define_expand "<ssse3_avx2>_pmulhrsw<mo
})
(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"
- [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
+ [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x,v")
(truncate:VI2_AVX2
(lshiftrt:<ssedoublemode>
(plus:<ssedoublemode>
(lshiftrt:<ssedoublemode>
(mult:<ssedoublemode>
(sign_extend:<ssedoublemode>
- (match_operand:VI2_AVX2 1 "vector_operand" "%0,v"))
+ (match_operand:VI2_AVX2 1 "vector_operand" "%0,x,v"))
(sign_extend:<ssedoublemode>
- (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))
+ (match_operand:VI2_AVX2 2 "vector_operand" "xBm,xm,vm")))
(const_int 14))
(match_operand:VI2_AVX2 3 "const1_operand"))
(const_int 1))))]
@@ -14175,12 +14175,13 @@ (define_insn "*<ssse3_avx2>_pmulhrsw<mod
&& ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
"@
pmulhrsw\t{%2, %0|%0, %2}
+ vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}
vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
- [(set_attr "isa" "noavx,avx")
+ [(set_attr "isa" "noavx,avx,avx512bw")
(set_attr "type" "sseimul")
- (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix_data16" "1,*,*")
(set_attr "prefix_extra" "1")
- (set_attr "prefix" "orig,maybe_evex")
+ (set_attr "prefix" "orig,maybe_evex,evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "*ssse3_pmulhrswv4hi3"
--- gcc/testsuite/gcc.target/i386/avx512vl-vpmulhrsw-3.c.jj 2016-05-13 15:21:31.422684540 +0200
+++ gcc/testsuite/gcc.target/i386/avx512vl-vpmulhrsw-3.c 2016-05-13 15:22:26.664898687 +0200
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */
+
+#include <x86intrin.h>
+
+void
+f1 (__m128i x, __m128i y)
+{
+ register __m128i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm_mulhrs_epi16 (a, b);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler-not "vpmulhrsw\[^\n\r]*xmm1\[67]" } } */
+
+void
+f2 (__m256i x, __m256i y)
+{
+ register __m256i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm256_mulhrs_epi16 (a, b);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler-not "vpmulhrsw\[^\n\r]*ymm1\[67]" } } */
--- gcc/testsuite/gcc.target/i386/avx512bw-vpmulhrsw-3.c.jj 2016-05-13 15:20:42.658349830 +0200
+++ gcc/testsuite/gcc.target/i386/avx512bw-vpmulhrsw-3.c 2016-05-13 15:15:17.000000000 +0200
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
+
+#include <x86intrin.h>
+
+void
+f1 (__m128i x, __m128i y)
+{
+ register __m128i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm_mulhrs_epi16 (a, b);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler "vpmulhrsw\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" } } */
+
+void
+f2 (__m256i x, __m256i y)
+{
+ register __m256i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm256_mulhrs_epi16 (a, b);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler "vpmulhrsw\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]" } } */
Jakub
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] Fix up vpmulhrsw for -mavx512vl -mno-avx512bw
2016-05-13 17:17 [PATCH] Fix up vpmulhrsw for -mavx512vl -mno-avx512bw Jakub Jelinek
@ 2016-05-18 8:51 ` Kirill Yukhin
0 siblings, 0 replies; 2+ messages in thread
From: Kirill Yukhin @ 2016-05-18 8:51 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, gcc-patches
On 13 May 19:16, Jakub Jelinek wrote:
> Hi!
>
> vpmulhrsw is AVX512BW & AVX512VL insn, so we shouldn't enable it just
> when AVX512VL is on.
>
> Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
> trunk?
>
> 2016-05-13 Jakub Jelinek <jakub@redhat.com>
>
> * config/i386/sse.md (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Use
> constraint x instead of v in second alternative, add avx512bw
> alternative.
>
> * gcc.target/i386/avx512vl-vpmulhrsw-3.c: New test.
> * gcc.target/i386/avx512bw-vpmulhrsw-3.c: New test.
OK.
--
Thanks, K
^ permalink raw reply [flat|nested] 2+ messages in thread
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