* [PATCH], Add support for PowerPC ISA 3.0 VNEGD/VNEGW instructions
@ 2016-05-18 18:30 Michael Meissner
2016-05-25 6:01 ` Segher Boessenkool
0 siblings, 1 reply; 2+ messages in thread
From: Michael Meissner @ 2016-05-18 18:30 UTC (permalink / raw)
To: gcc-patches, Segher Boessenkool, David Edelsohn, Bill Schmidt
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Unlike some of my patches, this is a fairly simple patch to add support for the
VNEGW and VNEGD instructions that were added in ISA 3.0. Note, ISA 3.0 does
not provide negation for V16QImode/V8HImode, just V4SImode/V2DImode.
I discovered that when we added ISA 2.07 support for V2DImode, we didn't
provide an expander for negv2di2, which I added with this patch.
[gcc]
2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/altivec.md (VNEG iterator): New iterator for
VNEGW/VNEGD instructions.
(p9_neg<mode>2): New insns for ISA 3.0 VNEGW/VNEGD.
(neg<mode>2): Add expander for V2DImode added in ISA 2.06, and
support for ISA 3.0 VNEGW/VNEGD instructions.
[gcc/testsuite]
2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-vneg.c: New test for ISA 3.0 VNEGW/VNEGD
instructions.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
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Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 236398)
+++ gcc/config/rs6000/altivec.md (.../gcc/config/rs6000) (working copy)
@@ -203,6 +203,9 @@ (define_mode_attr VP_small [(V2DI "V4SI"
(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")])
(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")])
n+;; Vector negate
+(define_mode_iterator VNEG [V4SI V2DI])
+
;; Vector move instructions.
(define_insn "*altivec_mov<mode>"
[(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v,*r")
@@ -2740,19 +2743,28 @@ (define_expand "reduc_plus_scal_<mode>"
DONE;
})
+(define_insn "*p9_neg<mode>2"
+ [(set (match_operand:VNEG 0 "altivec_register_operand" "=v")
+ (neg:VNEG (match_operand:VNEG 1 "altivec_register_operand" "v")))]
+ "TARGET_P9_VECTOR"
+ "vneg<VI_char> %0,%1"
+ [(set_attr "type" "vecsimple")])
+
(define_expand "neg<mode>2"
- [(use (match_operand:VI 0 "register_operand" ""))
- (use (match_operand:VI 1 "register_operand" ""))]
- "TARGET_ALTIVEC"
+ [(set (match_operand:VI2 0 "register_operand" "")
+ (neg:VI2 (match_operand:VI2 1 "register_operand" "")))]
+ "<VI_unit>"
"
{
- rtx vzero;
+ if (!TARGET_P9_VECTOR || (<MODE>mode != V4SImode && <MODE>mode != V2DImode))
+ {
+ rtx vzero;
- vzero = gen_reg_rtx (GET_MODE (operands[0]));
- emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
- emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
-
- DONE;
+ vzero = gen_reg_rtx (GET_MODE (operands[0]));
+ emit_move_insn (vzero, CONST0_RTX (<MODE>mode));
+ emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
+ DONE;
+ }
}")
(define_expand "udot_prod<mode>"
Index: gcc/testsuite/gcc.target/powerpc/p9-vneg.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-vneg.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/p9-vneg.c (.../gcc/testsuite/gcc.target/powerpc) (revision 236415)
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { powerpc64*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+/* Verify P9 vector negate instructions. */
+
+vector long long v2di_neg (vector long long a) { return -a; }
+vector int v4si_neg (vector int a) { return -a; }
+
+/* { dg-final { scan-assembler "vnegd" } } */
+/* { dg-final { scan-assembler "vnegw" } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH], Add support for PowerPC ISA 3.0 VNEGD/VNEGW instructions
2016-05-18 18:30 [PATCH], Add support for PowerPC ISA 3.0 VNEGD/VNEGW instructions Michael Meissner
@ 2016-05-25 6:01 ` Segher Boessenkool
0 siblings, 0 replies; 2+ messages in thread
From: Segher Boessenkool @ 2016-05-25 6:01 UTC (permalink / raw)
To: Michael Meissner, gcc-patches, David Edelsohn, Bill Schmidt
On Wed, May 18, 2016 at 02:30:31PM -0400, Michael Meissner wrote:
> Unlike some of my patches, this is a fairly simple patch to add support for the
> VNEGW and VNEGD instructions that were added in ISA 3.0. Note, ISA 3.0 does
> not provide negation for V16QImode/V8HImode, just V4SImode/V2DImode.
>
> I discovered that when we added ISA 2.07 support for V2DImode, we didn't
> provide an expander for negv2di2, which I added with this patch.
>
> [gcc]
> 2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * config/rs6000/altivec.md (VNEG iterator): New iterator for
> VNEGW/VNEGD instructions.
> (p9_neg<mode>2): New insns for ISA 3.0 VNEGW/VNEGD.
> (neg<mode>2): Add expander for V2DImode added in ISA 2.06, and
> support for ISA 3.0 VNEGW/VNEGD instructions.
>
> [gcc/testsuite]
> 2016-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * gcc.target/powerpc/p9-vneg.c: New test for ISA 3.0 VNEGW/VNEGD
> instructions.
I forgot to review this patch, sorry.
> Index: gcc/config/rs6000/altivec.md
> ===================================================================
> --- gcc/config/rs6000/altivec.md (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 236398)
> +++ gcc/config/rs6000/altivec.md (.../gcc/config/rs6000) (working copy)
> @@ -203,6 +203,9 @@ (define_mode_attr VP_small [(V2DI "V4SI"
> (define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")])
> (define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")])
>
> n+;; Vector negate
> +(define_mode_iterator VNEG [V4SI V2DI])
Your patch is mangled here, but you'll find out (it won't apply this way).
> (define_expand "neg<mode>2"
> - [(use (match_operand:VI 0 "register_operand" ""))
> - (use (match_operand:VI 1 "register_operand" ""))]
> - "TARGET_ALTIVEC"
> + [(set (match_operand:VI2 0 "register_operand" "")
> + (neg:VI2 (match_operand:VI2 1 "register_operand" "")))]
> + "<VI_unit>"
> "
> {
> - rtx vzero;
> + if (!TARGET_P9_VECTOR || (<MODE>mode != V4SImode && <MODE>mode != V2DImode))
> + {
> + rtx vzero;
>
> - vzero = gen_reg_rtx (GET_MODE (operands[0]));
> - emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
> - emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
> -
> - DONE;
> + vzero = gen_reg_rtx (GET_MODE (operands[0]));
> + emit_move_insn (vzero, CONST0_RTX (<MODE>mode));
> + emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
> + DONE;
> + }
> }")
Please remove the quotes around the C block as well, while you're here?
And a trailing space.
Okay for trunk, okay for 6 after a week or so.
Thanks,
Segher
^ permalink raw reply [flat|nested] 2+ messages in thread
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2016-05-25 6:01 ` Segher Boessenkool
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