* [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006
@ 2016-06-29 22:05 Michael Meissner
2016-06-29 23:16 ` Segher Boessenkool
0 siblings, 1 reply; 4+ messages in thread
From: Michael Meissner @ 2016-06-29 22:05 UTC (permalink / raw)
To: gcc-patches, Segher Boessenkool, David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 1795 bytes --]
Sigh, I forgot to attach the patch, and I also used the wrong bug number in my
previous patch.
As we discussed in the patch review, there were some issues with using %Y for
the ISA 3.0 instructions LXSD and STXSD.
I have rewritten the patch so that we have a new memory constraint (%wY) that
explicitly targets those instructions. I went back to the mov{DF,DD} patterns
and changed their use of %o to %wY.
I removed the test that was generated from the XalanNamespacesStack.cpp source
that showed up the problem.
I have bootstrapped this on a little endian power8 system and there were no
regressions in the test suite. I also built Spec 2006 for power9 with this
compiler, and the xalancbmk benchmark now builds. I will kick off a big endian
build on a power7 system.
Assuming there are no regressions in power7, are these patches ok to install in
the trunk, and backport to GCC 6.2 after a burn-in period?
2016-06-29 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/71677
* config/rs6000/constraints.md (wY constraint): New constraint to
match the requirements for the LXSD and STXSD instructions.
* config/rs6000/predicates.md (offsettable_mem_14bit_operand): New
predicate to match the requirements for the LXSD and STXSD
instructions.
* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case):
Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y'
to make sure that the bottom 2 bits of offset are 0, the address
form is offsettable, and no updating is done in the address mode.
(mov<mode>_hardfloat64, FMOVE64 case): Likewise.
(movdi_internal32): Likewise
(movdi_internal64): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: pr71677.patch02b --]
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Index: gcc/config/rs6000/constraints.md
===================================================================
--- gcc/config/rs6000/constraints.md (revision 237826)
+++ gcc/config/rs6000/constraints.md (working copy)
@@ -185,6 +185,11 @@ (define_constraint "wS"
"Vector constant that can be loaded with XXSPLTIB & sign extension."
(match_test "xxspltib_constant_split (op, mode)"))
+;; ISA 3.0 D-form instruction that has the bottom 2 bits 0 (LXSD or STXSD).
+(define_memory_constraint "wY"
+ "Offsettable memory operand, with bottom 2 bits 0"
+ (match_operand 0 "offsettable_mem_14bit_operand"))
+
;; Altivec style load/store that ignores the bottom bits of the address
(define_memory_constraint "wZ"
"Indexed or indirect memory operand, ignoring the bottom 4 bits"
Index: gcc/config/rs6000/predicates.md
===================================================================
--- gcc/config/rs6000/predicates.md (revision 237826)
+++ gcc/config/rs6000/predicates.md (working copy)
@@ -729,6 +729,15 @@ (define_predicate "offsettable_mem_opera
(and (match_operand 0 "memory_operand")
(match_test "offsettable_nonstrict_memref_p (op)")))
+;; Return 1 if the operand is an offsettable memory operand for ISA 3.0
+;; scalar LXSD/STXSD that must have the bottom 2 bits 0 and no update
+;; form
+(define_predicate "offsettable_mem_14bit_operand"
+ (and (match_operand 0 "memory_operand")
+ (match_test "offsettable_nonstrict_memref_p (op)")
+ (match_test "mem_operand_gpr (op, mode)")
+ (not (match_test "update_address_mem (op, mode)"))))
+
;; Return 1 if the operand is suitable for load/store quad memory.
;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
(define_predicate "quad_memory_operand"
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 237826)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -6773,8 +6773,8 @@ (define_split
;; except for 0.0 which can be created on VSX with an xor instruction.
(define_insn "*mov<mode>_hardfloat32"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,o,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
- (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,o,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -6812,8 +6812,8 @@ (define_insn "*mov<mode>_softfloat32"
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*mov<mode>_hardfloat64"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,o,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
- (match_operand:FMOVE64 1 "input_operand" "d,m,d,o,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7854,13 +7854,13 @@ (define_insn "p8_mfvsrd_4_disf"
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
"=Y, r, r, ?m, ?*d, ?*d,
- r, ?Y, ?Z, ?*wb, ?*wv, ?wi,
+ r, ?wY, ?Z, ?*wb, ?*wv, ?wi,
?wo, ?wo, ?wv, ?wi, ?wi, ?wv,
?wv")
(match_operand:DI 1 "input_operand"
"r, Y, r, d, m, d,
- IJKnGHF, wb, wv, Y, Z, wi,
+ IJKnGHF, wb, wv, wY, Z, wi,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -7930,14 +7930,14 @@ (define_split
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, r, r, r,
- ?m, ?*d, ?*d, ?Y, ?Z, ?*wb,
+ ?m, ?*d, ?*d, ?wY, ?Z, ?*wb,
?*wv, ?wi, ?wo, ?wo, ?wv, ?wi,
?wi, ?wv, ?wv, r, *h, *h,
?*r, ?*wg, ?*r, ?*wj")
(match_operand:DI 1 "input_operand"
"r, Y, r, I, L, nF,
- d, m, d, wb, wv, Y,
+ d, m, d, wb, wv, wY,
Z, wi, Oj, wM, OjwM, Oj,
wM, wS, wB, *h, r, 0,
wg, r, wj, r"))]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006
2016-06-29 22:05 [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006 Michael Meissner
@ 2016-06-29 23:16 ` Segher Boessenkool
2016-06-30 0:07 ` Michael Meissner
0 siblings, 1 reply; 4+ messages in thread
From: Segher Boessenkool @ 2016-06-29 23:16 UTC (permalink / raw)
To: Michael Meissner, gcc-patches, David Edelsohn, Bill Schmidt
On Wed, Jun 29, 2016 at 05:58:37PM -0400, Michael Meissner wrote:
> Assuming there are no regressions in power7, are these patches ok to install in
> the trunk, and backport to GCC 6.2 after a burn-in period?
Yes, this is fine, thanks for the changes. Okay for 6 too.
> * config/rs6000/constraints.md (wY constraint): New constraint to
> match the requirements for the LXSD and STXSD instructions.
It is nice that wY was still available :-)
Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006
2016-06-29 23:16 ` Segher Boessenkool
@ 2016-06-30 0:07 ` Michael Meissner
2016-06-30 4:05 ` Michael Meissner
0 siblings, 1 reply; 4+ messages in thread
From: Michael Meissner @ 2016-06-30 0:07 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Michael Meissner, gcc-patches, David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 1913 bytes --]
On Wed, Jun 29, 2016 at 06:06:04PM -0500, Segher Boessenkool wrote:
> On Wed, Jun 29, 2016 at 05:58:37PM -0400, Michael Meissner wrote:
> > Assuming there are no regressions in power7, are these patches ok to install in
> > the trunk, and backport to GCC 6.2 after a burn-in period?
>
> Yes, this is fine, thanks for the changes. Okay for 6 too.
>
> > * config/rs6000/constraints.md (wY constraint): New constraint to
> > match the requirements for the LXSD and STXSD instructions.
>
> It is nice that wY was still available :-)
:-)
Here is the patch I committed, subversion id 237864:
[gcc]
2016-06-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (const_0_to_7_operand): New
predicate, recognize 0..7.
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
support for doing extracts from V16QImode, V8HImode, V4SImode
under ISA 3.0.
* config/rs6000/vsx.md (VSX_EXTRACT_I): Mode iterator for ISA 3.0
vector extract support.
(VSX_EXTRACT_PREDICATE): Mode attribute to validate element number
for ISA 3.0 vector extract.
(VSX_EX): Constraints to use for ISA 3.0 vector extract.
(vsx_extract_<mode>, VSX_EXTRACT_I): Add support for doing
extracts of a constant element number from small integer vectors
on 64-bit ISA 3.0 systems.
(vsx_extract_<mode>_di): Likewise.
* config/rs6000/rs6000.h (TARGET_VEXTRACTUB): New target macro to
say when we can do ISA 3.0 vector extracts.
* config/rs6000/rs6000.md (stfiwx): Allow DImode in Altivec
registers, using the stxsiwx instruction.
[gcc/testsuite]
2016-06-29 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-extract-1.c: New file to test ISA 3.0
vector extract instructions.
* gcc.target/powerpc/p9-extract-2.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
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Index: gcc/config/rs6000/predicates.md
===================================================================
--- gcc/config/rs6000/predicates.md (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 237826)
+++ gcc/config/rs6000/predicates.md (.../gcc/config/rs6000) (working copy)
@@ -200,6 +200,11 @@ (define_predicate "const_2_to_3_operand"
(and (match_code "const_int")
(match_test "IN_RANGE (INTVAL (op), 2, 3)")))
+;; Match op = 0..7.
+(define_predicate "const_0_to_7_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
+
;; Match op = 0..15
(define_predicate "const_0_to_15_operand"
(and (match_code "const_int")
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 237826)
+++ gcc/config/rs6000/rs6000.c (.../gcc/config/rs6000) (working copy)
@@ -6916,6 +6916,30 @@ rs6000_expand_vector_extract (rtx target
case V4SFmode:
emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
return;
+ case V16QImode:
+ if (TARGET_VEXTRACTUB)
+ {
+ emit_insn (gen_vsx_extract_v16qi (target, vec, GEN_INT (elt)));
+ return;
+ }
+ else
+ break;
+ case V8HImode:
+ if (TARGET_VEXTRACTUB)
+ {
+ emit_insn (gen_vsx_extract_v8hi (target, vec, GEN_INT (elt)));
+ return;
+ }
+ else
+ break;
+ case V4SImode:
+ if (TARGET_VEXTRACTUB)
+ {
+ emit_insn (gen_vsx_extract_v4si (target, vec, GEN_INT (elt)));
+ return;
+ }
+ else
+ break;
}
}
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 237826)
+++ gcc/config/rs6000/vsx.md (.../gcc/config/rs6000) (working copy)
@@ -263,6 +263,21 @@ (define_mode_attr VS_64reg [(V2DF "ws")
(define_mode_iterator VSINT_84 [V4SI V2DI DI])
(define_mode_iterator VSINT_842 [V8HI V4SI V2DI])
+;; Iterator for ISA 3.0 vector extract/insert of integer vectors
+(define_mode_iterator VSX_EXTRACT_I [V16QI V8HI V4SI])
+
+;; Mode attribute to give the correct predicate for ISA 3.0 vector extract and
+;; insert to validate the operand number.
+(define_mode_attr VSX_EXTRACT_PREDICATE [(V16QI "const_0_to_15_operand")
+ (V8HI "const_0_to_7_operand")
+ (V4SI "const_0_to_3_operand")])
+
+;; Mode attribute to give the constraint for vector extract and insert
+;; operations.
+(define_mode_attr VSX_EX [(V16QI "v")
+ (V8HI "v")
+ (V4SI "wa")])
+
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@@ -2322,6 +2337,78 @@ (define_expand "vec_perm_const<mode>"
FAIL;
})
+;; Extraction of a single element in a small integer vector. None of the small
+;; types are currently allowed in a vector register, so we extract to a DImode
+;; and either do a direct move or store.
+(define_insn_and_split "vsx_extract_<mode>"
+ [(set (match_operand:<VS_scalar> 0 "nonimmediate_operand" "=r,Z")
+ (vec_select:<VS_scalar>
+ (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "<VSX_EX>,<VSX_EX>")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
+ (clobber (match_scratch:DI 3 "=<VSX_EX>,<VSX_EX>"))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
+ "#"
+ "&& (reload_completed || MEM_P (operands[0]))"
+ [(const_int 0)]
+{
+ rtx dest = operands[0];
+ rtx src = operands[1];
+ rtx element = operands[2];
+ rtx di_tmp = operands[3];
+
+ if (GET_CODE (di_tmp) == SCRATCH)
+ di_tmp = gen_reg_rtx (DImode);
+
+ emit_insn (gen_vsx_extract_<mode>_di (di_tmp, src, element));
+
+ if (REG_P (dest))
+ emit_move_insn (gen_rtx_REG (DImode, REGNO (dest)), di_tmp);
+ else if (SUBREG_P (dest))
+ emit_move_insn (gen_rtx_REG (DImode, subreg_regno (dest)), di_tmp);
+ else if (MEM_P (operands[0]))
+ {
+ if (can_create_pseudo_p ())
+ dest = rs6000_address_for_fpconvert (dest);
+
+ if (<MODE>mode == V16QImode)
+ emit_insn (gen_p9_stxsibx (dest, di_tmp));
+ else if (<MODE>mode == V8HImode)
+ emit_insn (gen_p9_stxsihx (dest, di_tmp));
+ else if (<MODE>mode == V4SImode)
+ emit_insn (gen_stfiwx (dest, di_tmp));
+ else
+ gcc_unreachable ();
+ }
+ else
+ gcc_unreachable ();
+
+ DONE;
+}
+ [(set_attr "type" "vecsimple,fpstore")])
+
+(define_insn "vsx_extract_<mode>_di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=<VSX_EX>")
+ (zero_extend:DI
+ (vec_select:<VS_scalar>
+ (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "<VSX_EX>")
+ (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")]))))]
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
+{
+ int element = INTVAL (operands[2]);
+ int unit_size = GET_MODE_UNIT_SIZE (<MODE>mode);
+ int offset = ((VECTOR_ELT_ORDER_BIG)
+ ? unit_size * element
+ : unit_size * (GET_MODE_NUNITS (<MODE>mode) - 1 - element));
+
+ operands[2] = GEN_INT (offset);
+ if (unit_size == 4)
+ return "xxextractuw %x0,%x1,%2";
+ else
+ return "vextractu<wd> %0,%1,%2";
+}
+ [(set_attr "type" "vecsimple")])
+
+
;; Expanders for builtins
(define_expand "vsx_mergel_<mode>"
[(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 237826)
+++ gcc/config/rs6000/rs6000.h (.../gcc/config/rs6000) (working copy)
@@ -599,6 +599,9 @@ extern int rs6000_vector_align[];
#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
&& TARGET_POWERPC64)
+#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
+ && TARGET_UPPER_REGS_DF \
+ && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
in power7, so conditionalize them on p8 features. TImode syncs need quad
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 237826)
+++ gcc/config/rs6000/rs6000.md (.../gcc/config/rs6000) (working copy)
@@ -5696,11 +5696,13 @@ (define_expand "lround<mode>di2"
; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx"
- [(set (match_operand:SI 0 "memory_operand" "=Z")
- (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
+ [(set (match_operand:SI 0 "memory_operand" "=Z,Z")
+ (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d,wv")]
UNSPEC_STFIWX))]
"TARGET_PPC_GFXOPT"
- "stfiwx %1,%y0"
+ "@
+ stfiwx %1,%y0
+ stxsiwx %x1,%y0"
[(set_attr "type" "fpstore")])
;; If we don't have a direct conversion to single precision, don't enable this
Property changes on: gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c
___________________________________________________________________
Modified: svn:mergeinfo
Merged /trunk/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c:r237394-237490,237609-237826
Property changes on: gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c
___________________________________________________________________
Modified: svn:mergeinfo
Merged /trunk/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c:r237394-237490,237609-237826
Index: gcc/testsuite/gcc.target/powerpc/p9-extract-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-extract-1.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/p9-extract-1.c (.../gcc/testsuite/gcc.target/powerpc) (revision 237858)
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+#include <altivec.h>
+
+int extract_int_0 (vector int a) { return vec_extract (a, 0); }
+int extract_int_3 (vector int a) { return vec_extract (a, 3); }
+
+int extract_short_0 (vector short a) { return vec_extract (a, 0); }
+int extract_short_3 (vector short a) { return vec_extract (a, 7); }
+
+int extract_schar_0 (vector signed char a) { return vec_extract (a, 0); }
+int extract_schar_3 (vector signed char a) { return vec_extract (a, 15); }
+
+/* { dg-final { scan-assembler "vextractub" } } */
+/* { dg-final { scan-assembler "vextractuh" } } */
+/* { dg-final { scan-assembler "xxextractuw" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "stxv" } } */
+/* { dg-final { scan-assembler-not "lwa" } } */
+/* { dg-final { scan-assembler-not "lwz" } } */
+/* { dg-final { scan-assembler-not "lha" } } */
+/* { dg-final { scan-assembler-not "lhz" } } */
Index: gcc/testsuite/gcc.target/powerpc/p9-extract-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-extract-2.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/p9-extract-2.c (.../gcc/testsuite/gcc.target/powerpc) (revision 237862)
@@ -0,0 +1,27 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+#include <altivec.h>
+
+void extract_int_0 (int *p, vector int a) { *p = vec_extract (a, 0); }
+void extract_int_3 (int *p, vector int a) { *p = vec_extract (a, 3); }
+
+void extract_short_0 (short *p, vector short a) { *p = vec_extract (a, 0); }
+void extract_short_3 (short *p, vector short a) { *p = vec_extract (a, 7); }
+
+void extract_schar_0 (signed char *p, vector signed char a) { *p = vec_extract (a, 0); }
+void extract_schar_3 (signed char *p, vector signed char a) { *p = vec_extract (a, 15); }
+
+/* { dg-final { scan-assembler "vextractub" } } */
+/* { dg-final { scan-assembler "vextractuh" } } */
+/* { dg-final { scan-assembler "xxextractuw" } } */
+/* { dg-final { scan-assembler "stxsibx" } } */
+/* { dg-final { scan-assembler "stxsihx" } } */
+/* { dg-final { scan-assembler "stfiwx\|stxsiwx" } } */
+/* { dg-final { scan-assembler-not "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "stxv" } } */
+/* { dg-final { scan-assembler-not "lwa" } } */
+/* { dg-final { scan-assembler-not "stw" } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006
2016-06-30 0:07 ` Michael Meissner
@ 2016-06-30 4:05 ` Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2016-06-30 4:05 UTC (permalink / raw)
To: Michael Meissner, Segher Boessenkool, gcc-patches,
David Edelsohn, Bill Schmidt
And yes, the reply was to the other patch in play (vector extract).
I think it is time to go home for the night, and I will commit the fix for PR
71677 tomorrow. :-)
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-06-30 0:07 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2016-06-29 22:05 [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006 Michael Meissner
2016-06-29 23:16 ` Segher Boessenkool
2016-06-30 0:07 ` Michael Meissner
2016-06-30 4:05 ` Michael Meissner
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