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[95.25.152.68]) by smtp.gmail.com with ESMTPSA id o76sm22080869wmg.16.2016.08.22.08.25.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Aug 2016 08:25:06 -0700 (PDT) Date: Mon, 22 Aug 2016 15:25:00 -0000 From: Kirill Yukhin To: Uros Bizjak Cc: "gcc-patches@gcc.gnu.org" Subject: Re: [RFT PATCH, i386]: Optimize zero-extensions from mask registers Message-ID: <20160822152454.GA25898@titus> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes X-SW-Source: 2016-08/txt/msg01545.txt.bz2 Hello Uroš, On 05 Aug 14:22, Uros Bizjak wrote: > Hello! > > Attached patch was inspired by assembly from PR 72805 testcase. > Currently, the compiler generates: > > test: > vpternlogd $0xFF, %zmm0, %zmm0, %zmm0 > vpxord %zmm1, %zmm1, %zmm1 > vpcmpd $1, %zmm1, %zmm0, %k1 > kmovw %k1, %eax > movzwl %ax, %eax > ret > > Please note that kmovw already zero-extended from a mask register. > > 2016-08-05 Uros Bizjak > > * config/i386/i386.md (*zero_extendsidi2): Add (*r,*k) alternative. > (zero_extenddi2): Ditto. > (*zero_extendsi2): Ditto. > (*zero_extendqihi2): Ditto. > > Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. > > The patch is in RFT state, since I have no means to test AVX512 stuff. > Kirill, can someone from Intel please test the patch? I gave a try to your patch and see no regressions or bootstrap failures on i386/x86_64 (run on SDE). -- Thanks, K > > Uros. > Index: config/i386/i386.md > =================================================================== > --- config/i386/i386.md (revision 239166) > +++ config/i386/i386.md (working copy) > @@ -3688,10 +3688,10 @@ > > (define_insn "*zero_extendsidi2" > [(set (match_operand:DI 0 "nonimmediate_operand" > - "=r,?r,?o,r ,o,?*Ym,?!*y,?r ,?r,?*Yi,?*x") > + "=r,?r,?o,r ,o,?*Ym,?!*y,?r ,?r,?*Yi,?*x,*r") > (zero_extend:DI > (match_operand:SI 1 "x86_64_zext_operand" > - "0 ,rm,r ,rmWz,0,r ,m ,*Yj,*x,r ,m")))] > + "0 ,rm,r ,rmWz,0,r ,m ,*Yj,*x,r ,m ,*k")))] > "" > { > switch (get_attr_type (insn)) > @@ -3717,6 +3717,9 @@ > > return "%vmovd\t{%1, %0|%0, %1}"; > > + case TYPE_MSKMOV: > + return "kmovd\t{%1, %k0|%k0, %1}"; > + > default: > gcc_unreachable (); > } > @@ -3724,7 +3727,7 @@ > [(set (attr "isa") > (cond [(eq_attr "alternative" "0,1,2") > (const_string "nox64") > - (eq_attr "alternative" "3,7") > + (eq_attr "alternative" "3,7,11") > (const_string "x64") > (eq_attr "alternative" "8") > (const_string "x64_sse4") > @@ -3741,6 +3744,8 @@ > (const_string "ssemov") > (eq_attr "alternative" "8") > (const_string "sselog1") > + (eq_attr "alternative" "11") > + (const_string "mskmov") > ] > (const_string "imovx"))) > (set (attr "prefix_extra") > @@ -3792,12 +3797,14 @@ > "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") > > (define_insn "zero_extenddi2" > - [(set (match_operand:DI 0 "register_operand" "=r") > + [(set (match_operand:DI 0 "register_operand" "=r,*r") > (zero_extend:DI > - (match_operand:SWI12 1 "nonimmediate_operand" "m")))] > + (match_operand:SWI12 1 "nonimmediate_operand" "m,*k")))] > "TARGET_64BIT" > - "movz{l|x}\t{%1, %k0|%k0, %1}" > - [(set_attr "type" "imovx") > + "@ > + movz{l|x}\t{%1, %k0|%k0, %1} > + kmov\t{%1, %k0|%k0, %1}" > + [(set_attr "type" "imovx,mskmov") > (set_attr "mode" "SI")]) > > (define_expand "zero_extendsi2" > @@ -3841,13 +3848,15 @@ > (set_attr "mode" "SI")]) > > (define_insn "*zero_extendsi2" > - [(set (match_operand:SI 0 "register_operand" "=r") > + [(set (match_operand:SI 0 "register_operand" "=r,*r") > (zero_extend:SI > - (match_operand:SWI12 1 "nonimmediate_operand" "m")))] > + (match_operand:SWI12 1 "nonimmediate_operand" "m,*k")))] > "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))" > - "movz{l|x}\t{%1, %0|%0, %1}" > - [(set_attr "type" "imovx") > - (set_attr "mode" "SI")]) > + "@ > + movz{l|x}\t{%1, %0|%0, %1} > + kmov\t{%1, %0|%0, %1}" > + [(set_attr "type" "imovx,mskmov") > + (set_attr "mode" "SI,")]) > > (define_expand "zero_extendqihi2" > [(set (match_operand:HI 0 "register_operand") > @@ -3890,12 +3899,14 @@ > > ; zero extend to SImode to avoid partial register stalls > (define_insn "*zero_extendqihi2" > - [(set (match_operand:HI 0 "register_operand" "=r") > - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] > + [(set (match_operand:HI 0 "register_operand" "=r,*r") > + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,*k")))] > "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))" > - "movz{bl|x}\t{%1, %k0|%k0, %1}" > - [(set_attr "type" "imovx") > - (set_attr "mode" "SI")]) > + "@ > + movz{bl|x}\t{%1, %k0|%k0, %1} > + kmovb\t{%1, %k0|%k0, %1}" > + [(set_attr "type" "imovx,mskmov") > + (set_attr "mode" "SI,QI")]) > > (define_insn_and_split "*zext_doubleword_and" > [(set (match_operand:DI 0 "register_operand" "=&")