From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 35106 invoked by alias); 27 Sep 2016 14:09:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 35080 invoked by uid 89); 27 Sep 2016 14:09:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM autolearn=no version=3.3.2 spammy=asl, ror X-HELO: mail-wm0-f41.google.com Received: from mail-wm0-f41.google.com (HELO mail-wm0-f41.google.com) (74.125.82.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 27 Sep 2016 14:09:31 +0000 Received: by mail-wm0-f41.google.com with SMTP id l132so15318450wmf.1 for ; Tue, 27 Sep 2016 07:09:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=+ry8t6wMTZlLPXQmnPLSNygTvMx3HFJBKajRUOenPHU=; b=VH4jr0t+KXw+BgjLTYvLmo0+5bcxyBNgdjFvvh+d+416A4F/U16MdvthOT0PGmv1dK H3uVvuK6QAB71O1CWRxUHDbtlFo6fVtn+pq+O3nxyE/szdB3ULqAt7sIzlbUlJlQEiJI hdTbbXAFfN3pF4PkvEpb28q20prkl0TszryhRzzHwi+DIq5LC/09DB6MF6uWaok3kems 6wdStsp5b4n2Jj9XJbLiUoLvAVv5tDYhjtapgPkxj/uO66F8o7JKAu34H8YBltrVrU6s 2iOn1mhz3h+vjn/S5Kzl3k2zIcmJovTB9oU1K9lZz3Xmuy47SlnF/zpHFJu0ELQnEMbl AZKg== X-Gm-Message-State: AA6/9RmBo+XWtxFqg1D7Dpxcqg34Iwr7455WeZQO6mpZ+1PeZVAPrxfOLxkCSW1rcc1OjA== X-Received: by 10.28.140.5 with SMTP id o5mr3384321wmd.13.1474985369082; Tue, 27 Sep 2016 07:09:29 -0700 (PDT) Received: from localhost (host86-165-30-128.range86-165.btcentralplus.com. [86.165.30.128]) by smtp.gmail.com with ESMTPSA id p71sm17040872wmf.9.2016.09.27.07.09.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Sep 2016 07:09:28 -0700 (PDT) Date: Tue, 27 Sep 2016 14:29:00 -0000 From: Andrew Burgess To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org, gnu@amylaar.uk, Francois.Bedard@synopsys.com Subject: Re: [PATCH] [ARC] Add simple shift/rotate ops. Message-ID: <20160927140911.GJ6374@embecosm.com> References: <1466154788-5054-1-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1466154788-5054-1-git-send-email-claziss@synopsys.com> X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.6.1 (2016-04-27) X-IsSubscribed: yes X-SW-Source: 2016-09/txt/msg01998.txt.bz2 * Claudiu Zissulescu [2016-06-17 11:13:08 +0200]: > Basic ARC cpus are having only simple shift operations. Here they are. > > OK to apply? This looks good to me. Thanks, Andrew > > gcc/ > 2016-06-09 Claudiu Zissulescu > > * config/arc/arc.md (*rotrsi3_cnt1): New pattern, > (*ashlsi2_cnt1, *lshrsi3_cnt1, *ashrsi3_cnt1): Likewise. > --- > gcc/config/arc/arc.md | 40 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 852f0e0..a095ba1 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -6219,6 +6219,46 @@ > (zero_extract:SI (match_dup 1) (match_dup 5) (match_dup 7)))]) > (match_dup 1)]) > > +(define_insn "*rotrsi3_cnt1" > + [(set (match_operand:SI 0 "dest_reg_operand" "=w") > + (rotatert:SI (match_operand:SI 1 "register_operand" "c") > + (const_int 1)))] > + "" > + "ror %0,%1%&" > + [(set_attr "type" "shift") > + (set_attr "predicable" "no") > + (set_attr "length" "4")]) > + > +(define_insn "*ashlsi2_cnt1" > + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") > + (ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c") > + (const_int 1)))] > + "" > + "asl%? %0,%1%&" > + [(set_attr "type" "shift") > + (set_attr "iscompact" "maybe,false") > + (set_attr "predicable" "no,no")]) > + > +(define_insn "*lshrsi3_cnt1" > + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") > + (lshiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c") > + (const_int 1)))] > + "" > + "lsr%? %0,%1%&" > + [(set_attr "type" "shift") > + (set_attr "iscompact" "maybe,false") > + (set_attr "predicable" "no,no")]) > + > +(define_insn "*ashrsi3_cnt1" > + [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") > + (ashiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c") > + (const_int 1)))] > + "" > + "asr%? %0,%1%&" > + [(set_attr "type" "shift") > + (set_attr "iscompact" "maybe,false") > + (set_attr "predicable" "no,no")]) > + > ;; include the arc-FPX instructions > (include "fpx.md") > > -- > 1.9.1 >