* [AArch64][0/14] ARMv8.2-A FP16 extension support
@ 2016-07-07 16:13 Jiong Wang
2016-07-25 11:26 ` James Greenhalgh
0 siblings, 1 reply; 5+ messages in thread
From: Jiong Wang @ 2016-07-07 16:13 UTC (permalink / raw)
To: GCC Patches
Hello,
As a follow up of
https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01240.html,
This patch set adds ARMv8.2-A FP16 scalar and vector intrinsics support,
gcc middle-end will also be aware of some standard operations that some
instructions can be auto-generated.
According to ACLE, ARMv8.2-A FP16 intrinsics for AArch64 is superset of
intrinsics for AArch32, so all those intrinsic related testcases,
particularly those under the directory advsimd-intrinsics, are also
appliable to AArch64. This patch set has only included those testcases
that are exclusive for AArch64.
---
Jiong Wang (14)
ARMv8.2-A FP16 data processing intrinsics
ARMv8.2-A FP16 one operand vector intrinsics
ARMv8.2-A FP16 two operands vector intrinsics
ARMv8.2-A FP16 three operands vector intrinsics
ARMv8.2-A FP16 lane vector intrinsics
ARMv8.2-A FP16 reduction vector intrinsics
ARMv8.2-A FP16 one operand scalar intrinsics
ARMv8.2-A FP16 two operands scalar intrinsics
ARMv8.2-A FP16 three operands scalar intrinsics
ARMv8.2-A FP16 lane scalar intrinsics
ARMv8.2-A FP16 testsuite selector
ARMv8.2-A testsuite for new data movement intrinsics
ARMv8.2-A testsuite for new vector intrinsics
ARMv8.2-A testsuite for new scalar intrinsics
gcc/config.gcc | 2 +-
gcc/config/aarch64/aarch64-builtins.c | 5 +
gcc/config/aarch64/aarch64-simd-builtins.def | 161 ++++++++++++----
gcc/config/aarch64/aarch64-simd.md | 352 +++++++++++----------------
gcc/config/aarch64/aarch64.c | 16 ++
gcc/config/aarch64/aarch64.md | 161 ++++++++++------
gcc/config/aarch64/arm_fp16.h | 579 +++++++++
gcc/config/aarch64/arm_neon.h | 1380 +++++++++++++++------
gcc/config/aarch64/iterators.md | 88 +++++++--
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h | 16 +-
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc | 1 +
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c | 44 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c | 20 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c | 20 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c | 20 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c | 20 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c | 21 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c | 20 ++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c | 25 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c | 25 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c | 25 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c | 25 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c | 46 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c | 46 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c | 46 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c | 46 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c | 29 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c | 29 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c | 29 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c | 29 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c | 23 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdiv_f16_1.c | 86 +++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c | 119 +++++++++++-
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vduph_lane.c | 137 +++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c | 908 +++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmas_n_f16_1.c | 469 +++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c | 143 ++++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxh_f16_1.c | 34 ++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c | 131 +++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxv_f16_1.c | 131 +++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminh_f16_1.c | 34 ++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmv_f16_1.c | 131 +++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminv_f16_1.c | 131 +++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane_f16_1.c | 454 ++++++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c | 90 +++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_f16_1.c | 84 ++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c | 452 +++++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulx_n_f16_1.c | 177 +++++++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_f16_1.c | 50 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c | 91 +++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c | 114 +++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpeh_f16_1.c | 42 ++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpsh_f16_1.c | 50 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrecpxh_f16_1.c | 32 ++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndi_f16_1.c | 71 +++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c | 30 +++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c | 50 +++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrt_f16_1.c | 72 +++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c | 263 +++++++++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c | 259 +++++++++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c | 263 +++++++++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 50 +++--
89 files changed, 8743 insertions(+), 359 deletions(-)
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [AArch64][0/14] ARMv8.2-A FP16 extension support
2016-07-07 16:13 [AArch64][0/14] ARMv8.2-A FP16 extension support Jiong Wang
@ 2016-07-25 11:26 ` James Greenhalgh
2016-09-27 16:40 ` Jiong Wang
0 siblings, 1 reply; 5+ messages in thread
From: James Greenhalgh @ 2016-07-25 11:26 UTC (permalink / raw)
To: Jiong Wang; +Cc: GCC Patches, nd
On Thu, Jul 07, 2016 at 05:12:48PM +0100, Jiong Wang wrote:
> Hello,
>
> As a follow up of
>
> https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01240.html,
>
> This patch set adds ARMv8.2-A FP16 scalar and vector intrinsics support,
> gcc middle-end will also be aware of some standard operations that some
> instructions can be auto-generated.
>
> According to ACLE, ARMv8.2-A FP16 intrinsics for AArch64 is superset of
> intrinsics for AArch32, so all those intrinsic related testcases,
> particularly those under the directory advsimd-intrinsics, are also
> appliable to AArch64. This patch set has only included those testcases
> that are exclusive for AArch64.
>
> Jiong Wang (14)
> ARMv8.2-A FP16 data processing intrinsics
> ARMv8.2-A FP16 one operand vector intrinsics
> ARMv8.2-A FP16 two operands vector intrinsics
> ARMv8.2-A FP16 three operands vector intrinsics
> ARMv8.2-A FP16 lane vector intrinsics
> ARMv8.2-A FP16 reduction vector intrinsics
> ARMv8.2-A FP16 one operand scalar intrinsics
> ARMv8.2-A FP16 two operands scalar intrinsics
> ARMv8.2-A FP16 three operands scalar intrinsics
> ARMv8.2-A FP16 lane scalar intrinsics
At this point, I've OKed the first 10 patches in the series, these represent
the functional changes to the compiler. I'm leaving the testsuite patches
for now, as they depend on testsuite changes that have yet to be approved
for the ARM port.
To save you from having to continue to rebase the functional parts of this
patch while you wait for review of the ARM changes, I would be OK with you
committing them now, on the understanding that you'll continue to check
the testsuite in the time between now and the testsuite changes are approved,
and that you'll fix any issues that you find.
> ARMv8.2-A FP16 testsuite selector
> ARMv8.2-A testsuite for new data movement intrinsics
> ARMv8.2-A testsuite for new vector intrinsics
> ARMv8.2-A testsuite for new scalar intrinsics
I've taken a brief look through these testsuite changes and they look OK
to me. I'll revisit them properly once I've seen the ARM patches go in.
Thanks,
James
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [AArch64][0/14] ARMv8.2-A FP16 extension support
2016-07-25 11:26 ` James Greenhalgh
@ 2016-09-27 16:40 ` Jiong Wang
2016-10-05 16:44 ` Jiong Wang
0 siblings, 1 reply; 5+ messages in thread
From: Jiong Wang @ 2016-09-27 16:40 UTC (permalink / raw)
To: James Greenhalgh; +Cc: GCC Patches
On 25/07/16 12:26, James Greenhalgh wrote:
> On Thu, Jul 07, 2016 at 05:12:48PM +0100, Jiong Wang wrote:
>> Hello,
>>
>> As a follow up of
>>
>> https://gcc.gnu.org/ml/gcc-patches/2016-05/msg01240.html,
>>
>> This patch set adds ARMv8.2-A FP16 scalar and vector intrinsics support,
>> gcc middle-end will also be aware of some standard operations that some
>> instructions can be auto-generated.
>>
>> According to ACLE, ARMv8.2-A FP16 intrinsics for AArch64 is superset of
>> intrinsics for AArch32, so all those intrinsic related testcases,
>> particularly those under the directory advsimd-intrinsics, are also
>> appliable to AArch64. This patch set has only included those testcases
>> that are exclusive for AArch64.
>>
>> Jiong Wang (14)
>> ARMv8.2-A FP16 data processing intrinsics
>> ARMv8.2-A FP16 one operand vector intrinsics
>> ARMv8.2-A FP16 two operands vector intrinsics
>> ARMv8.2-A FP16 three operands vector intrinsics
>> ARMv8.2-A FP16 lane vector intrinsics
>> ARMv8.2-A FP16 reduction vector intrinsics
>> ARMv8.2-A FP16 one operand scalar intrinsics
>> ARMv8.2-A FP16 two operands scalar intrinsics
>> ARMv8.2-A FP16 three operands scalar intrinsics
>> ARMv8.2-A FP16 lane scalar intrinsics
> At this point, I've OKed the first 10 patches in the series, these represent
> the functional changes to the compiler. I'm leaving the testsuite patches
> for now, as they depend on testsuite changes that have yet to be approved
> for the ARM port.
>
> To save you from having to continue to rebase the functional parts of this
> patch while you wait for review of the ARM changes, I would be OK with you
> committing them now, on the understanding that you'll continue to check
> the testsuite in the time between now and the testsuite changes are approved,
> and that you'll fix any issues that you find.
>
>> ARMv8.2-A FP16 testsuite selector
>> ARMv8.2-A testsuite for new data movement intrinsics
>> ARMv8.2-A testsuite for new vector intrinsics
>> ARMv8.2-A testsuite for new scalar intrinsics
>
> I've taken a brief look through these testsuite changes and they look OK
> to me. I'll revisit them properly once I've seen the ARM patches go in.
Now as ARM patches have gone in around r240427, I have done a quick
confirmation
on the status of these four pending testsuite patches:
https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00337.html
https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00338.html
https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00339.html
https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00340.html
The result is they applies cleanly on gcc trunk, and there is no
regression on
AArch64 native regression test. Testcases enabled without requirement
of FP16
all passed.
I will give a final run on ARM native board and AArch64 emulation
environment
with ARMv8.2-A FP16 enabled. (Have done this before, just in case something
changed during these days)
OK for trunk if there is no regression?
Thanks
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [AArch64][0/14] ARMv8.2-A FP16 extension support
2016-09-27 16:40 ` Jiong Wang
@ 2016-10-05 16:44 ` Jiong Wang
2016-10-10 10:38 ` James Greenhalgh
0 siblings, 1 reply; 5+ messages in thread
From: Jiong Wang @ 2016-10-05 16:44 UTC (permalink / raw)
To: James Greenhalgh; +Cc: GCC Patches
[-- Attachment #1: Type: text/plain, Size: 1242 bytes --]
On 27/09/16 17:03, Jiong Wang wrote:
>
> Now as ARM patches have gone in around r240427, I have done a quick
confirmation
> on the status of these four pending testsuite patches:
>
> https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00337.html
> https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00338.html
> https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00339.html
> https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00340.html
>
> The result is they applies cleanly on gcc trunk, and there is no
regression on
> AArch64 native regression test. Testcases enabled without
requirement of FP16
> all passed.
>
> I will give a final run on ARM native board and AArch64 emulation
environment
> with ARMv8.2-A FP16 enabled. (Have done this before, just in case
something
> changed during these days)
>
> OK for trunk if there is no regression?
>
> Thanks
Finished the final tests on emulator with FP16 enabled.
* No regression on AARCH64, all new testcases passed.
* No regression on AARCH32, part of these new testcases UNRESOLVED
because
they should be skipped on AARCH32, fixed by the attached trivial patch
which I will merge into the 4th patch (no affect on changelog).
OK to commit these patches?
[-- Attachment #2: skip-aarch32.patch --]
[-- Type: text/x-patch, Size: 7540 bytes --]
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c
index f8c8c79..0bebec7 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c
index 23c11a4..68ce599 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c
index ae4c8b5..1b5a09b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c
index 56a6533..766c783 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c
index fb54e96..8f5c14b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c
index 57c765c..ccfecf4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c
index f9a5bbe..161c7a0 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c
index a5997cc..2d3cd8a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c
index f0a37e8..0d35385 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c
index 41e57a2..ca23e3f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c
index e19eb51..f51cac3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c
index 6d09db9..57901c8 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c
index f81c900..3218873 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c
index 00f6923..af6a5b6 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
/* { dg-add-options arm_v8_2a_fp16_scalar } */
+/* { dg-skip-if "" { arm*-*-* } } */
#include <arm_fp16.h>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [AArch64][0/14] ARMv8.2-A FP16 extension support
2016-10-05 16:44 ` Jiong Wang
@ 2016-10-10 10:38 ` James Greenhalgh
0 siblings, 0 replies; 5+ messages in thread
From: James Greenhalgh @ 2016-10-10 10:38 UTC (permalink / raw)
To: Jiong Wang; +Cc: GCC Patches, nd
On Wed, Oct 05, 2016 at 05:44:08PM +0100, Jiong Wang wrote:
> On 27/09/16 17:03, Jiong Wang wrote:
> >
> > Now as ARM patches have gone in around r240427, I have done a
> quick confirmation
> > on the status of these four pending testsuite patches:
> >
> > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00337.html
> > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00338.html
> > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00339.html
> > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00340.html
> >
> > The result is they applies cleanly on gcc trunk, and there is no
> regression on
> > AArch64 native regression test. Testcases enabled without
> requirement of FP16
> > all passed.
> >
> > I will give a final run on ARM native board and AArch64 emulation
> environment
> > with ARMv8.2-A FP16 enabled. (Have done this before, just in case
> something
> > changed during these days)
> >
> > OK for trunk if there is no regression?
> >
> > Thanks
>
> Finished the final tests on emulator with FP16 enabled.
>
> * No regression on AARCH64, all new testcases passed.
> * No regression on AARCH32, part of these new testcases UNRESOLVED
> because
> they should be skipped on AARCH32, fixed by the attached trivial patch
> which I will merge into the 4th patch (no affect on changelog).
>
> OK to commit these patches?
And to be explicit, this is OK too.
Thanks for the tests!
Cheers,
James
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-10-10 10:38 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-07 16:13 [AArch64][0/14] ARMv8.2-A FP16 extension support Jiong Wang
2016-07-25 11:26 ` James Greenhalgh
2016-09-27 16:40 ` Jiong Wang
2016-10-05 16:44 ` Jiong Wang
2016-10-10 10:38 ` James Greenhalgh
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