Re: [PATCH] combine: Omit redundant AND in change_zero_ext.

[Segher Boessenkool <segher@kernel.crashing.org>]

On Wed, Dec 14, 2016 at 11:01:47AM +0100, Dominik Vogt wrote:
> This is another micro-optimisation in change_zero_ext.  If an
> 
>   (and (lshiftrt ... (N)) (M))
> 
> generated by change_zero_ext is equivalent to just
> 
>   (lshiftrt ... (N))
> 
> (because the AND constant selects the N rightmost bits of the
> result), strip off the AND.
> 
> _But_ I'm still not completely convinced whether this is a good
> idea.  It may become necessary to add md patterns to deal with
> just the LSHIFTRT.  On the other hand it saves the need for
> another special case in change_zero_ext, and a less obvious, very
> specific risbg pattern on s390 

For PowerPC we should already have all such patterns with a "bare" shift
(they can be created in other ways, too).

> Bootstrapped and regression tested on s390x and s390.  (Targets
> with risbg-like instructions (Power, others?) may need some
> tuning.)

But, it is also possible I missed some.  So please wait until I have
tested it.


> diff --git a/gcc/combine.c b/gcc/combine.c
> index 19851a2..5ebf31c 100644
> --- a/gcc/combine.c
> +++ b/gcc/combine.c
> @@ -11280,8 +11280,13 @@ change_zero_ext (rtx pat)
>        else
>  	continue;
>  
> -      wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
> -      x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
> +      if (!(GET_CODE (x) == LSHIFTRT
> +	    && CONST_INT_P (XEXP (x, 1))
> +	    && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
> +	{
> +	  wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
> +	  x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
> +	}

One could argue that this should have been an lshiftrt in the first place
then, not a zero_ext*.  Hrm.


Segher