From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 73272 invoked by alias); 15 Dec 2016 08:56:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 73253 invoked by uid 89); 15 Dec 2016 08:56:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_LOW,RCVD_IN_SEMBACKSCATTER autolearn=no version=3.3.2 spammy=zero_extract, ui64, 48PM, 48pm X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 08:55:59 +0000 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uBF8t6v2041101 for ; Thu, 15 Dec 2016 03:55:58 -0500 Received: from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107]) by mx0b-001b2d01.pphosted.com with ESMTP id 27bn7f1nu4-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 15 Dec 2016 03:55:57 -0500 Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Reply-To: vogt@linux.vnet.ibm.com Mail-Followup-To: vogt@linux.vnet.ibm.com, Segher Boessenkool , gcc-patches@gcc.gnu.org, Andreas Krebbel References: <20161214100147.GA3427@linux.vnet.ibm.com> <20161214193248.GY30845@gate.crashing.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161214193248.GY30845@gate.crashing.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16121508-0040-0000-0000-0000031F5674 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16121508-0041-0000-0000-00001E3F2C3D Message-Id: <20161215085552.GA17600@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-12-15_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1612150143 X-SW-Source: 2016-12/txt/msg01339.txt.bz2 On Wed, Dec 14, 2016 at 01:32:48PM -0600, Segher Boessenkool wrote: > On Wed, Dec 14, 2016 at 11:01:47AM +0100, Dominik Vogt wrote: > > This is another micro-optimisation in change_zero_ext. If an > > > > (and (lshiftrt ... (N)) (M)) > > > > generated by change_zero_ext is equivalent to just > > > > (lshiftrt ... (N)) > > > > (because the AND constant selects the N rightmost bits of the > > result), strip off the AND. > > > > _But_ I'm still not completely convinced whether this is a good > > idea. It may become necessary to add md patterns to deal with > > just the LSHIFTRT. On the other hand it saves the need for > > another special case in change_zero_ext, and a less obvious, very > > specific risbg pattern on s390 > > For PowerPC we should already have all such patterns with a "bare" shift > (they can be created in other ways, too). > > > Bootstrapped and regression tested on s390x and s390. (Targets > > with risbg-like instructions (Power, others?) may need some > > tuning.) > > But, it is also possible I missed some. So please wait until I have > tested it. > > > > diff --git a/gcc/combine.c b/gcc/combine.c > > index 19851a2..5ebf31c 100644 > > --- a/gcc/combine.c > > +++ b/gcc/combine.c > > @@ -11280,8 +11280,13 @@ change_zero_ext (rtx pat) > > else > > continue; > > > > - wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode)); > > - x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode)); > > + if (!(GET_CODE (x) == LSHIFTRT > > + && CONST_INT_P (XEXP (x, 1)) > > + && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode))) > > + { > > + wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode)); > > + x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode)); > > + } > > One could argue that this should have been an lshiftrt in the first place > then, not a zero_ext*. Hrm. This one void g2(ui64 *pl, i32 seed) { seed = 69607 * seed; pl[0] = (seed >> 8) & 0xffffff; } generates (zero_extract:DI (reg:SI 75 [ seed ]) (const_int 24 [0x18]) (const_int 0 [0])) on s390x. Ciao Dominik ^_^ ^_^ -- Dominik Vogt IBM Germany