[PATCH] Fix -m3dnowa (PR target/79569)

[Jakub Jelinek <jakub@redhat.com>]

Hi!

-m3dnowa is an undocumented option that always errors out.
The following patch fixes it and makes it do the obvious thing.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

2017-02-17  Jakub Jelinek  <jakub@redhat.com>

	PR target/79569
	* config/i386/i386.opt (m3dnowa): Replace Undocumented with Report.
	* common/config/i386/i386-common.c (OPTION_MASK_ISA_3DNOW_A_SET): Define.
	(ix86_handle_option): Handle OPT_m3dnowa.
	* doc/invoke.texi (-m3dnowa): Document.
	* doc/extend.texi (__builtin_ia32_pmulhuw, __builtin_ia32_pf2iw): Use
	-m3dnowa instead of -m3dnow -march=athlon.

	* gcc.target/i386/3dnowA-3.c: New test.

--- gcc/config/i386/i386.opt.jj	2017-01-16 12:28:35.000000000 +0100
+++ gcc/config/i386/i386.opt	2017-02-17 11:23:06.674671212 +0100
@@ -614,7 +614,7 @@ Target Report Mask(ISA_3DNOW) Var(ix86_i
 Support 3DNow! built-in functions.
 
 m3dnowa
-Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
+Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
 Support Athlon 3Dnow! built-in functions.
 
 msse
--- gcc/common/config/i386/i386-common.c.jj	2017-01-12 22:29:00.000000000 +0100
+++ gcc/common/config/i386/i386-common.c	2017-02-17 10:55:20.023152107 +0100
@@ -35,6 +35,8 @@ along with GCC; see the file COPYING3.
 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
 #define OPTION_MASK_ISA_3DNOW_SET \
   (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
+#define OPTION_MASK_ISA_3DNOW_A_SET \
+  (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
 
 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
 #define OPTION_MASK_ISA_SSE2_SET \
@@ -291,7 +293,17 @@ ix86_handle_option (struct gcc_options *
       return true;
 
     case OPT_m3dnowa:
-      return false;
+      if (value)
+	{
+	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
+	}
+      return true;
 
     case OPT_msse:
       if (value)
--- gcc/doc/invoke.texi.jj	2017-02-16 12:00:36.000000000 +0100
+++ gcc/doc/invoke.texi	2017-02-17 11:31:38.772731527 +0100
@@ -1188,9 +1188,9 @@ See RS/6000 and PowerPC Options.
 -mavx512bw  -mavx512dq  -mavx512ifma  -mavx512vbmi  -msha  -maes @gol
 -mpclmul  -mfsgsbase  -mrdrnd  -mf16c  -mfma @gol
 -mprefetchwt1  -mclflushopt  -mxsavec  -mxsaves @gol
--msse4a  -m3dnow  -mpopcnt  -mabm  -mbmi  -mtbm  -mfma4  -mxop  -mlzcnt @gol
--mbmi2  -mfxsr  -mxsave  -mxsaveopt  -mrtm  -mlwp  -mmpx  -mmwaitx @gol
--mclzero  -mpku  -mthreads @gol
+-msse4a  -m3dnow  -m3dnowa  -mpopcnt  -mabm  -mbmi  -mtbm  -mfma4  -mxop @gol
+-mlzcnt  -mbmi2  -mfxsr  -mxsave  -mxsaveopt  -mrtm  -mlwp  -mmpx  @gol
+-mmwaitx  -mclzero  -mpku  -mthreads @gol
 -mms-bitfields  -mno-align-stringops  -minline-all-stringops @gol
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg} @gol
 -mmemcpy-strategy=@var{strategy}  -mmemset-strategy=@var{strategy} @gol
@@ -25004,6 +25004,9 @@ preferred alignment to @option{-mpreferr
 @itemx -m3dnow
 @opindex m3dnow
 @need 200
+@itemx -m3dnowa
+@opindex m3dnowa
+@need 200
 @itemx -mpopcnt
 @opindex mpopcnt
 @need 200
@@ -25053,7 +25056,7 @@ These switches enable the use of instruc
 SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
 SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
 AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR,
-XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU or 3DNow!@:
+XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, 3DNow!@: or enhanced 3DNow!@:
 extended instruction sets.  Each has a corresponding @option{-mno-} option
 to disable use of these instructions.
 
--- gcc/doc/extend.texi.jj	2017-02-13 12:20:51.000000000 +0100
+++ gcc/doc/extend.texi	2017-02-17 12:02:22.195884349 +0100
@@ -19513,9 +19513,8 @@ v2si __builtin_ia32_psradi (v2si, int)
 @end smallexample
 
 The following built-in functions are made available either with
-@option{-msse}, or with a combination of @option{-m3dnow} and
-@option{-march=athlon}.  All of them generate the machine
-instruction that is part of the name.
+@option{-msse}, or with @option{-m3dnowa}.  All of them generate
+the machine instruction that is part of the name.
 
 @smallexample
 v4hi __builtin_ia32_pmulhuw (v4hi, v4hi)
@@ -20615,9 +20614,8 @@ v2sf __builtin_ia32_pi2fd (v2si)
 v4hi __builtin_ia32_pmulhrw (v4hi, v4hi)
 @end smallexample
 
-The following built-in functions are available when both @option{-m3dnow}
-and @option{-march=athlon} are used.  All of them generate the machine
-instruction that is part of the name.
+The following built-in functions are available when @option{-m3dnowa} is used.
+All of them generate the machine instruction that is part of the name.
 
 @smallexample
 v2si __builtin_ia32_pf2iw (v2sf)
--- gcc/testsuite/gcc.target/i386/3dnowA-3.c.jj	2017-02-17 11:36:17.772950662 +0100
+++ gcc/testsuite/gcc.target/i386/3dnowA-3.c	2017-02-17 11:36:07.987083275 +0100
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -m3dnowa" } */
+
+#include <mm3dnow.h>
+
+__m64
+foo (__m64 x, __m64 y)
+{
+  return _m_pfnacc (x, y);
+}

	Jakub