From: James Greenhalgh <james.greenhalgh@arm.com>
To: "Hurugalawadi, Naveen" <Naveen.Hurugalawadi@cavium.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"Pinski, Andrew" <Andrew.Pinski@cavium.com>,
Marcus Shawcroft <marcus.shawcroft@arm.com>,
Richard Earnshaw <Richard.Earnshaw@arm.com>, <nd@arm.com>
Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion
Date: Wed, 08 Mar 2017 18:04:00 -0000 [thread overview]
Message-ID: <20170308180359.GD25712@arm.com> (raw)
In-Reply-To: <CO2PR07MB2694CB39F815C51139D35101832C0@CO2PR07MB2694.namprd07.prod.outlook.com>
On Mon, Mar 06, 2017 at 05:10:10AM +0000, Hurugalawadi, Naveen wrote:
> Hi,
>
> Please find attached the patch that implements alu_branch fusion
> for AArch64.
> The patch doesn't change spec but improve other benchmarks.
>
> Bootstrapped and Regression tested on aarch64-thunder-linux.
> Please review the patch and let us know if its okay for Stage-1?
This description is insufficient for me to review this patch - in
particular I'd need more detail on what types of instruction pairs you
are trying to fuse. From inspection you will be trying to fuse any
ALU operation with an unconditional direct branch. Is that what you
intend?
i.e. you are looking to fuse instruction sequences like:
add x0, x1, #5
b .L3
csel x0, x1, x1, gt
b .L4
Have I understood that right?
> + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH)
> + && any_uncondjump_p (curr))
> + {
> + /* These types correspond to the reservation "vulcan_alu_basic" for
> + Broadcom Vulcan: these are ALU operations that produce a single uop
> + during instruction decoding. */
This comment looks incorrect - there is no vulcan_alu_basic reservation
in trunk GCC.
Thanks,
James
next prev parent reply other threads:[~2017-03-08 18:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-06 5:12 Hurugalawadi, Naveen
2017-03-08 18:04 ` James Greenhalgh [this message]
2017-03-09 6:22 ` Hurugalawadi, Naveen
2017-03-09 10:22 ` James Greenhalgh
2017-03-15 5:33 ` Hurugalawadi, Naveen
2017-03-15 9:23 ` Kyrill Tkachov
2017-03-15 10:04 ` Hurugalawadi, Naveen
[not found] <VI1PR0802MB26218E2C0940948518A0571783210@VI1PR0802MB2621.eurprd08.prod.outlook.com>
2017-03-15 15:20 ` Wilco Dijkstra
2017-03-21 5:37 ` Andrew Pinski
2017-03-27 7:33 ` Hurugalawadi, Naveen
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