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Wed, 8 Mar 2017 18:04:00 +0000 Date: Wed, 08 Mar 2017 18:04:00 -0000 From: James Greenhalgh To: "Hurugalawadi, Naveen" CC: "gcc-patches@gcc.gnu.org" , "Pinski, Andrew" , Marcus Shawcroft , Richard Earnshaw , Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion Message-ID: <20170308180359.GD25712@arm.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:217.140.96.140;IPV:CAL;SCL:-1;CTRY:GB;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(39410400002)(39860400002)(39840400002)(39450400003)(39850400002)(2980300002)(438002)(199003)(24454002)(189002)(6286002)(6246003)(8936002)(50986999)(2950100002)(106466001)(36756003)(5660300001)(76176999)(110136004)(33656002)(356003)(305945005)(7696004)(83506001)(38730400002)(4326008)(55016002)(54906002)(23726003)(54356999)(47776003)(189998001)(50466002)(1076002)(4001350100001)(46406003)(5890100001)(8676002)(77096006)(2906002)(97756001)(104016004)(229853002)(86362001)(18370500001);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR08MB0350;H:nebula.arm.com;FPR:;SPF:Pass;MLV:sfv;A:1;MX:1;LANG:en; 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This description is insufficient for me to review this patch - in particular I'd need more detail on what types of instruction pairs you are trying to fuse. From inspection you will be trying to fuse any ALU operation with an unconditional direct branch. Is that what you intend? i.e. you are looking to fuse instruction sequences like: add x0, x1, #5 b .L3 csel x0, x1, x1, gt b .L4 Have I understood that right? > + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) > + && any_uncondjump_p (curr)) > + { > + /* These types correspond to the reservation "vulcan_alu_basic" for > + Broadcom Vulcan: these are ALU operations that produce a single uop > + during instruction decoding. */ This comment looks incorrect - there is no vulcan_alu_basic reservation in trunk GCC. Thanks, James