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From: James Greenhalgh <james.greenhalgh@arm.com>
To: "Hurugalawadi, Naveen" <Naveen.Hurugalawadi@cavium.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
	"Pinski, Andrew"	<Andrew.Pinski@cavium.com>,
	Marcus Shawcroft <marcus.shawcroft@arm.com>,
	Richard Earnshaw <Richard.Earnshaw@arm.com>,
	"nd@arm.com" <nd@arm.com>
Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion
Date: Thu, 09 Mar 2017 10:22:00 -0000	[thread overview]
Message-ID: <20170309102200.GA40049@arm.com> (raw)
In-Reply-To: <CO2PR07MB269496BC132974C448BFC7BB83210@CO2PR07MB2694.namprd07.prod.outlook.com>

On Thu, Mar 09, 2017 at 06:22:33AM +0000, Hurugalawadi, Naveen wrote:
> Hi James,
> 
> Thanks for the review and your comments.
> 
> >> I'd need more detail on what types of instruction pairs you
> >> are trying to fuse. 
> 
> The documentation mentions it as follows:-
> Single uop ALU instruction may fuse with adjacent branch instruction in the
> same bundle
> 
> >> This comment looks incorrect - there is no vulcan_alu_basic reservation
> 
> Modified as per comment.
> 
> Please let us know if the description is sufficient?

My reason for asking is that the instruction fusion implemented in LLVM
( lib/Target/AArch64/AArch64MacroFusion.cpp::shouldScheduleAdjacent ) is
between ALU instructions and conditional branches, while this patch fuses
ALU instructions and unconditional branches. I'm trying to understand why
there is a discrepancy, and consequently whether this patch is correct.

Your clarification helps, but it would be useful to know which sort of
branches you are actually targeting and to fix the disagreement between
this patch and LLVM.

Thanks,
James

  reply	other threads:[~2017-03-09 10:22 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-06  5:12 Hurugalawadi, Naveen
2017-03-08 18:04 ` James Greenhalgh
2017-03-09  6:22   ` Hurugalawadi, Naveen
2017-03-09 10:22     ` James Greenhalgh [this message]
2017-03-15  5:33       ` Hurugalawadi, Naveen
2017-03-15  9:23         ` Kyrill Tkachov
2017-03-15 10:04           ` Hurugalawadi, Naveen
     [not found] <VI1PR0802MB26218E2C0940948518A0571783210@VI1PR0802MB2621.eurprd08.prod.outlook.com>
2017-03-15 15:20 ` Wilco Dijkstra
2017-03-21  5:37   ` Andrew Pinski
2017-03-27  7:33     ` Hurugalawadi, Naveen

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