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From: Prakhar Bahuguna <prakhar.bahuguna@arm.com>
To: Christophe Lyon <christophe.lyon@linaro.org>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>, nd <nd@arm.com>
Subject: Re: [PING][PATCH, GCC/ARM] Only test tls-disable-literal-pool.c if target supports native TLS
Date: Tue, 30 May 2017 12:29:00 -0000	[thread overview]
Message-ID: <20170530122440.4hjoxta747sl7244@e107464-lin.cambridge.arm.com> (raw)
In-Reply-To: <CAKdteOakatN-BOfPbQ4RdBQxYS=m+63x3i9OTkrEsPRELiCzQg@mail.gmail.com>

On 30/05/2017 14:11:22, Christophe Lyon wrote:
> On 30 May 2017 at 09:44, Prakhar Bahuguna <prakhar.bahuguna@arm.com> wrote:
> > On 29/05/2017 14:23:05, Christophe Lyon wrote:
> >> On 19 May 2017 at 14:29, Prakhar Bahuguna <prakhar.bahuguna@arm.com> wrote:
> >> > On 11/05/2017 14:54:37, Prakhar Bahuguna wrote:
> >> >> tls-disable-literal-pool.c should only be run if the toolchain and target
> >> >> support native thread-local storage rather than emulated TLS. This patch also
> >> >> improves the matching of the error message.
> >> >>
> >> >> testsuite/ChangeLog:
> >> >>
> >> >> 2017-05-11  Prakhar Bahuguna  <prakhar.bahuguna@arm.com>
> >> >>
> >> >>       * gcc.target/arm/tls-disable-literal-pool.c: Change
> >> >>       require-effective-target to tls_native.
> >> >>       Move dg-error to return statement line and change to dg-message.
> >> >>
> >> >> Testing done: Regression testing for ARMv7-M with a TLS-enabled toolchain and a
> >> >> TLS-disabled toolchain.
> >> >>
> >>
> >> Hi,
> >> Can you share more details on the configuration you used?
> >> In my testing, the only cortex-M config I have is arm-none-eabi
> >> --with-cpu=cortex-m3.
> >> Since arm-none-eabi means native-tls is disabled, this test is skipped.
> >> A constraint for me is that m3 was the only cortex-m cpu supported by qemu the
> >> last time I checked.
> >>
> >> Thanks,
> >>
> >> Christophe
> >>
> >
> > Hi Christophe,
> >
> > For a regular arm-none-eabi build, TLS is indeed disabled and the test should
> > be skipped. The diagnostic and test is meant to catch instances where the
> > toolchain has been built with native TLS enabled. This can be done either by
> > explicitly passing the --enable-tls configure flag for arm-none-eabi, or by
> 
> This didn't occur to me: what does --target arm-none-eabi --enable-tls actually
> means in terms of functionality? Do you use newlib +  a suitable kernel to
> provide thread support? Or are all the tls-related GCC tests compile-only,
> and we do not need a setup with proper thread support to actually test this?
> 

Hi Christophe, the test is compile-only. Threading isn't really a thing in the
context of bare-metal code on a microcontroller, but this diagnostic is there
to prevent the compiler from generating garbage assembly even if the user is
going out of their way to do something nonsensical. The test exists to validate
that the diagnostic triggers under such conditions.

> > using an arm-none-linux-gnueabi[hf] toolchain and testing against an M-profile
> > target.
> I guess you use a board for that? As I'm using qemu (user mode) for GCC testing,
> I'm not sure how I could test such a configuration given that qemu
> does not support
> any v7m processor to my knowledge.

As above, the execution target does not matter as there is no code to execute.
The compiler should simply error out if told to compile code with thread-local
variables and literal pools disabled.

-- 

Prakhar Bahuguna

      reply	other threads:[~2017-05-30 12:24 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-19 12:33 Prakhar Bahuguna
2017-05-19 12:51 ` Kyrill Tkachov
2017-05-29 12:56 ` Christophe Lyon
2017-05-30  7:47   ` Prakhar Bahuguna
2017-05-30 12:12     ` Christophe Lyon
2017-05-30 12:29       ` Prakhar Bahuguna [this message]

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