From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23873 invoked by alias); 31 May 2017 14:49:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 2222 invoked by uid 89); 31 May 2017 14:48:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=zero_extract, ccc X-HELO: mail-wm0-f48.google.com Received: from mail-wm0-f48.google.com (HELO mail-wm0-f48.google.com) (74.125.82.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 31 May 2017 14:48:20 +0000 Received: by mail-wm0-f48.google.com with SMTP id 7so121630296wmo.1 for ; Wed, 31 May 2017 07:48:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=frCcNgHcdI7vs8LKDV6MoeOKBDz30wkQZGT6ZjY5UY8=; b=FZdOkmNEBcyPks9N/fwZpWd12UXmahQj4JBbyWqJISsVm2Y0TJV3U27sZy2cwMvqLG fNWY5AHxBnE07fRWlaiv2EaEs6sGCGnvKZNWOOiDvTjvsEYztT0r9T+QYC9BJ51jjDGf Cvu9F8Q9TWj4tnjZShu6xCiPiFYhiANTPX+hxsx8Gh923XXOf91/nblkaSfhsKTr9/Lv 5kam/bPq/ETahujAuBQkuBnIvsA8+RG09mQ83YyEVweb7K4ZU3C0U8AEfWF/j8d6ekpG aorlwcYkisNeUr+vEF8GWiNk7lhXbgn0wtBrHoBZkHx2OfRhlYu44R+OKFsY+OTZHipk qvtQ== X-Gm-Message-State: AODbwcDLK2nTRJbdfDdOc2wbFaGsvxUDi8JSQwoStwC4Mjg2aNWG59iQ /lF2a73ZWoEm03E2 X-Received: by 10.28.50.65 with SMTP id y62mr5889826wmy.5.1496242095746; Wed, 31 May 2017 07:48:15 -0700 (PDT) Received: from localhost (host86-164-133-102.range86-164.btcentralplus.com. [86.164.133.102]) by smtp.gmail.com with ESMTPSA id y3sm11948457wrd.23.2017.05.31.07.48.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 May 2017 07:48:14 -0700 (PDT) Date: Wed, 31 May 2017 14:52:00 -0000 From: Andrew Burgess To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org, Francois.Bedard@synopsys.com Subject: Re: [PATCH 2/7] [ARC] Avoid use of hard registers before reg-alloc. Message-ID: <20170531144803.GD25719@embecosm.com> References: <1495189862-20533-1-git-send-email-claziss@synopsys.com> <1495189862-20533-3-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1495189862-20533-3-git-send-email-claziss@synopsys.com> X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.6.1 (2016-04-27) X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg02374.txt.bz2 * Claudiu Zissulescu [2017-05-19 12:30:57 +0200]: > gcc/ > 2017-04-10 Claudiu Zissulescu > > * config/arc/arc.md (mulsi3): Avoid use of hard registers before > reg-alloc when having mul64 or mul32x16 instructions. > (mulsidi3): Likewise. > (umulsidi3): Likewise. > (mulsi32x16): New pattern. > (mulsi64): Likewise. > (mulsidi64): Likewise. > (umulsidi64): Likewise. > (MUL32x16_REG): Define. > (mul64_600): Use MUL32x16_REG. > (mac64_600): Likewise. > (umul64_600): Likewise. > (umac64_600): Likewise. Looks good, thanks, Andrew > --- > gcc/config/arc/arc.md | 168 +++++++++++++++++++++++++++++++++++--------------- > 1 file changed, 119 insertions(+), 49 deletions(-) > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index db5867c..c0ad86c 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -176,6 +176,7 @@ > (ILINK2_REGNUM 30) > (RETURN_ADDR_REGNUM 31) > (MUL64_OUT_REG 58) > + (MUL32x16_REG 56) > (ARCV2_ACC 58) > > (LP_COUNT 60) > @@ -1940,29 +1941,17 @@ > } > else if (TARGET_MUL64_SET) > { > - emit_insn (gen_mulsi_600 (operands[1], operands[2], > - gen_mlo (), gen_mhi ())); > - emit_move_insn (operands[0], gen_mlo ()); > - DONE; > + rtx tmp = gen_reg_rtx (SImode); > + emit_insn (gen_mulsi64 (tmp, operands[1], operands[2])); > + emit_move_insn (operands[0], tmp); > + DONE; > } > else if (TARGET_MULMAC_32BY16_SET) > { > - if (immediate_operand (operands[2], SImode) > - && INTVAL (operands[2]) >= 0 > - && INTVAL (operands[2]) <= 65535) > - { > - emit_insn (gen_umul_600 (operands[1], operands[2], > - gen_acc2 (), gen_acc1 ())); > - emit_move_insn (operands[0], gen_acc2 ()); > - DONE; > - } > - operands[2] = force_reg (SImode, operands[2]); > - emit_insn (gen_umul_600 (operands[1], operands[2], > - gen_acc2 (), gen_acc1 ())); > - emit_insn (gen_mac_600 (operands[1], operands[2], > - gen_acc2 (), gen_acc1 ())); > - emit_move_insn (operands[0], gen_acc2 ()); > - DONE; > + rtx tmp = gen_reg_rtx (SImode); > + emit_insn (gen_mulsi32x16 (tmp, operands[1], operands[2])); > + emit_move_insn (operands[0], tmp); > + DONE; > } > else > { > @@ -1974,6 +1963,35 @@ > } > }) > > +(define_insn_and_split "mulsi32x16" > + [(set (match_operand:SI 0 "register_operand" "=w") > + (mult:SI (match_operand:SI 1 "register_operand" "%c") > + (match_operand:SI 2 "nonmemory_operand" "ci"))) > + (clobber (reg:DI MUL32x16_REG))] > + "TARGET_MULMAC_32BY16_SET" > + "#" > + "TARGET_MULMAC_32BY16_SET && reload_completed" > + [(const_int 0)] > + { > + if (immediate_operand (operands[2], SImode) > + && INTVAL (operands[2]) >= 0 > + && INTVAL (operands[2]) <= 65535) > + { > + emit_insn (gen_umul_600 (operands[1], operands[2], > + gen_acc2 (), gen_acc1 ())); > + emit_move_insn (operands[0], gen_acc2 ()); > + DONE; > + } > + emit_insn (gen_umul_600 (operands[1], operands[2], > + gen_acc2 (), gen_acc1 ())); > + emit_insn (gen_mac_600 (operands[1], operands[2], > + gen_acc2 (), gen_acc1 ())); > + emit_move_insn (operands[0], gen_acc2 ()); > + DONE; > + } > + [(set_attr "type" "multi") > + (set_attr "length" "8")]) > + > ; mululw conditional execution without a LIMM clobbers an input register; > ; we'd need a different pattern to describe this. > ; To make the conditional execution valid for the LIMM alternative, we > @@ -2011,6 +2029,24 @@ > (set_attr "predicable" "no, no, yes") > (set_attr "cond" "nocond, canuse_limm, canuse")]) > > +(define_insn_and_split "mulsi64" > + [(set (match_operand:SI 0 "register_operand" "=w") > + (mult:SI (match_operand:SI 1 "register_operand" "%c") > + (match_operand:SI 2 "nonmemory_operand" "ci"))) > + (clobber (reg:DI MUL64_OUT_REG))] > + "TARGET_MUL64_SET" > + "#" > + "TARGET_MUL64_SET && reload_completed" > + [(const_int 0)] > +{ > + emit_insn (gen_mulsi_600 (operands[1], operands[2], > + gen_mlo (), gen_mhi ())); > + emit_move_insn (operands[0], gen_mlo ()); > + DONE; > +} > + [(set_attr "type" "multi") > + (set_attr "length" "8")]) > + > (define_insn "mulsi_600" > [(set (match_operand:SI 2 "mlo_operand" "") > (mult:SI (match_operand:SI 0 "register_operand" "%Rcq#q,c,c,c") > @@ -2155,8 +2191,7 @@ > (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) > (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" ""))))] > "TARGET_ANY_MPY" > -" > -{ > + { > if (TARGET_PLUS_MACD) > { > if (CONST_INT_P (operands[2])) > @@ -2189,18 +2224,37 @@ > } > else if (TARGET_MULMAC_32BY16_SET) > { > - rtx result_hi = gen_highpart(SImode, operands[0]); > - rtx result_low = gen_lowpart(SImode, operands[0]); > - > - emit_insn (gen_mul64_600 (operands[1], operands[2])); > - emit_insn (gen_mac64_600 (result_hi, operands[1], operands[2])); > - emit_move_insn (result_low, gen_acc2 ()); > + operands[2] = force_reg (SImode, operands[2]); > + emit_insn (gen_mulsidi64 (operands[0], operands[1], operands[2])); > DONE; > } > -}") > + operands[2] = force_reg (SImode, operands[2]); > + }) > + > +(define_insn_and_split "mulsidi64" > + [(set (match_operand:DI 0 "register_operand" "=w") > + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%c")) > + (sign_extend:DI (match_operand:SI 2 "extend_operand" "ci")))) > + (clobber (reg:DI MUL32x16_REG))] > + "TARGET_MULMAC_32BY16_SET" > + "#" > + "TARGET_MULMAC_32BY16_SET && reload_completed" > + [(const_int 0)] > + { > + rtx result_hi = gen_highpart (SImode, operands[0]); > + rtx result_low = gen_lowpart (SImode, operands[0]); > + > + emit_insn (gen_mul64_600 (operands[1], operands[2])); > + emit_insn (gen_mac64_600 (result_hi, operands[1], operands[2])); > + emit_move_insn (result_low, gen_acc2 ()); > + DONE; > + } > + [(set_attr "type" "multi") > + (set_attr "length" "8")]) > + > > (define_insn "mul64_600" > - [(set (reg:DI 56) > + [(set (reg:DI MUL32x16_REG) > (mult:DI (sign_extend:DI (match_operand:SI 0 "register_operand" > "c,c,c")) > (zero_extract:DI (match_operand:SI 1 "nonmemory_operand" > @@ -2218,14 +2272,14 @@ > > ;; ??? check if this is canonical rtl > (define_insn "mac64_600" > - [(set (reg:DI 56) > + [(set (reg:DI MUL32x16_REG) > (plus:DI > (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "c,c,c")) > (ashift:DI > (sign_extract:DI (match_operand:SI 2 "nonmemory_operand" "c,L,Cal") > (const_int 16) (const_int 16)) > (const_int 16))) > - (reg:DI 56))) > + (reg:DI MUL32x16_REG))) > (set (match_operand:SI 0 "register_operand" "=w,w,w") > (zero_extract:SI > (plus:DI > @@ -2234,7 +2288,7 @@ > (sign_extract:DI (match_dup 2) > (const_int 16) (const_int 16)) > (const_int 16))) > - (reg:DI 56)) > + (reg:DI MUL32x16_REG)) > (const_int 32) (const_int 32)))] > "TARGET_MULMAC_32BY16_SET" > "machlw%? %0, %1, %2" > @@ -2428,20 +2482,14 @@ > } > else if (TARGET_MUL64_SET) > { > - emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2])); > + operands[2] = force_reg (SImode, operands[2]); > + emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2])); > DONE; > } > else if (TARGET_MULMAC_32BY16_SET) > { > - rtx result_hi = gen_reg_rtx (SImode); > - rtx result_low = gen_reg_rtx (SImode); > - > - result_hi = gen_highpart(SImode , operands[0]); > - result_low = gen_lowpart(SImode , operands[0]); > - > - emit_insn (gen_umul64_600 (operands[1], operands[2])); > - emit_insn (gen_umac64_600 (result_hi, operands[1], operands[2])); > - emit_move_insn (result_low, gen_acc2 ()); > + operands[2] = force_reg (SImode, operands[2]); > + emit_insn (gen_umulsidi64 (operands[0], operands[1], operands[2])); > DONE; > } > else > @@ -2454,8 +2502,32 @@ > } > }) > > +(define_insn_and_split "umulsidi64" > + [(set (match_operand:DI 0 "register_operand" "=w") > + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c")) > + (zero_extend:DI (match_operand:SI 2 "extend_operand" "ci")))) > + (clobber (reg:DI MUL32x16_REG))] > + "TARGET_MULMAC_32BY16_SET" > + "#" > + "TARGET_MULMAC_32BY16_SET && reload_completed" > + [(const_int 0)] > + { > + rtx result_hi; > + rtx result_low; > + > + result_hi = gen_highpart (SImode, operands[0]); > + result_low = gen_lowpart (SImode, operands[0]); > + > + emit_insn (gen_umul64_600 (operands[1], operands[2])); > + emit_insn (gen_umac64_600 (result_hi, operands[1], operands[2])); > + emit_move_insn (result_low, gen_acc2 ()); > + DONE; > + } > + [(set_attr "type" "multi") > + (set_attr "length" "8")]) > + > (define_insn "umul64_600" > - [(set (reg:DI 56) > + [(set (reg:DI MUL32x16_REG) > (mult:DI (zero_extend:DI (match_operand:SI 0 "register_operand" > "c,c,c")) > (zero_extract:DI (match_operand:SI 1 "nonmemory_operand" > @@ -2472,14 +2544,14 @@ > > > (define_insn "umac64_600" > - [(set (reg:DI 56) > + [(set (reg:DI MUL32x16_REG) > (plus:DI > (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "c,c,c")) > (ashift:DI > (zero_extract:DI (match_operand:SI 2 "nonmemory_operand" "c,L,Cal") > (const_int 16) (const_int 16)) > (const_int 16))) > - (reg:DI 56))) > + (reg:DI MUL32x16_REG))) > (set (match_operand:SI 0 "register_operand" "=w,w,w") > (zero_extract:SI > (plus:DI > @@ -2488,7 +2560,7 @@ > (zero_extract:DI (match_dup 2) > (const_int 16) (const_int 16)) > (const_int 16))) > - (reg:DI 56)) > + (reg:DI MUL32x16_REG)) > (const_int 32) (const_int 32)))] > "TARGET_MULMAC_32BY16_SET" > "machulw%? %0, %1, %2" > @@ -2497,8 +2569,6 @@ > (set_attr "predicable" "no,no,yes") > (set_attr "cond" "nocond, canuse_limm, canuse")]) > > - > - > ;; DI <- DI(unsigned SI) * DI(unsigned SI) > (define_insn_and_split "umulsidi3_700" > [(set (match_operand:DI 0 "dest_reg_operand" "=&r") > -- > 1.9.1 >