* [PATCH][AArch64] Add crypto_pmull attribute @ 2017-03-06 5:11 Hurugalawadi, Naveen 2017-03-09 10:51 ` James Greenhalgh 0 siblings, 1 reply; 10+ messages in thread From: Hurugalawadi, Naveen @ 2017-03-06 5:11 UTC (permalink / raw) To: gcc-patches Cc: Pinski, Andrew, James Greenhalgh, Marcus Shawcroft, Richard Earnshaw [-- Attachment #1: Type: text/plain, Size: 862 bytes --] Hi, Please find attached the patch that adds "crypto_pmull" for AArch64. Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06 Julian Brown <julian@codesourcery.com> Naveen H.S <Naveen.Hurugalawadi@cavium.com> * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi) (aarch64_crypto_pmullv2di): Change type attribute to crypto_pmull. * config/aarch64/thunderx2t99.md (thunderx2t99_pmull): New reservation. * config/arm/cortex-a57.md (cortex_a57_neon_type): Add crypto_pmull to attribute type list for neon_multiply. * config/arm/crypto.md (crypto_vmullp64): Change type to crypto_pmull. * config/arm/types.md (crypto_pmull): Add. * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to attribute type list. [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #2: crypto_pmull.patch --] [-- Type: text/x-patch; name="crypto_pmull.patch", Size: 2977 bytes --] diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b61f79a..338b9f8 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5818,7 +5818,7 @@ UNSPEC_PMULL))] "TARGET_SIMD && TARGET_CRYPTO" "pmull\\t%0.1q, %1.1d, %2.1d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "aarch64_crypto_pmullv2di" @@ -5828,5 +5828,5 @@ UNSPEC_PMULL2))] "TARGET_SIMD && TARGET_CRYPTO" "pmull2\\t%0.1q, %1.2d, %2.2d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index 0dd7199..67011ac 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -441,3 +441,8 @@ (and (eq_attr "tune" "thunderx2t99") (eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q")) "thunderx2t99_ls01,thunderx2t99_f01") + +(define_insn_reservation "thunderx2t99_pmull" 5 + (and (eq_attr "tune" "thunderx2t99") + (eq_attr "type" "crypto_pmull")) + "thunderx2t99_f1") diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index fd30758..ebf4a49 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -76,7 +76,7 @@ neon_mul_h_scalar_long, neon_mul_s_scalar_long,\ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long") + neon_sat_mul_s_scalar_long, crypto_pmull") (const_string "neon_multiply") (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\ neon_mul_h_scalar_q, neon_mul_s_scalar_q,\ diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index 46b0715..a5e558b 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -81,7 +81,7 @@ UNSPEC_VMULLP64))] "TARGET_CRYPTO" "vmull.p64\\t%q0, %P1, %P2" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "crypto_<crypto_pattern>" diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index b0b375c..253f496 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -539,6 +539,7 @@ ; crypto_sha1_slow ; crypto_sha256_fast ; crypto_sha256_slow +; crypto_pmull ; ; The classification below is for coprocessor instructions ; @@ -1078,6 +1079,7 @@ crypto_sha1_slow,\ crypto_sha256_fast,\ crypto_sha256_slow,\ + crypto_pmull,\ coproc" (const_string "untyped")) diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index 62a0732..34a13f4 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -527,5 +527,6 @@ (define_insn_reservation "xgene1_neon_pmull" 5 (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_mul_d_long,\ - ")) + crypto_pmull,\ + ")) "xgene1_decode2op") ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH][AArch64] Add crypto_pmull attribute 2017-03-06 5:11 [PATCH][AArch64] Add crypto_pmull attribute Hurugalawadi, Naveen @ 2017-03-09 10:51 ` James Greenhalgh 2017-03-10 6:37 ` Hurugalawadi, Naveen 0 siblings, 1 reply; 10+ messages in thread From: James Greenhalgh @ 2017-03-09 10:51 UTC (permalink / raw) To: Hurugalawadi, Naveen Cc: gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd On Mon, Mar 06, 2017 at 05:09:34AM +0000, Hurugalawadi, Naveen wrote: > Hi, > > Please find attached the patch that adds "crypto_pmull" for AArch64. > > Bootstrapped and Regression tested on aarch64-thunder-linux. > > Please review the patch and let us know if its okay for Stage-1? > > Thanks, > Naveen > > 2017-03-06 Julian Brown <julian@codesourcery.com> > Naveen H.S <Naveen.Hurugalawadi@cavium.com> > > * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi) > (aarch64_crypto_pmullv2di): Change type attribute to crypto_pmull. > * config/aarch64/thunderx2t99.md (thunderx2t99_pmull): New > reservation. > * config/arm/cortex-a57.md (cortex_a57_neon_type): Add crypto_pmull to > attribute type list for neon_multiply. You need to do this for all cores which might be affected by this change, i.e. all those which model neon_mul_d_long. I see: gcc/config/arm/cortex-a53.md gcc/config/arm/exynos-m1.md Which your patch doesn't touch, but which have modeling for neon_mul_d_long. Thanks, James > * config/arm/crypto.md (crypto_vmullp64): Change type to crypto_pmull. > * config/arm/types.md (crypto_pmull): Add. > * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to > attribute type list. ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH][AArch64] Add crypto_pmull attribute 2017-03-09 10:51 ` James Greenhalgh @ 2017-03-10 6:37 ` Hurugalawadi, Naveen 2017-04-25 7:10 ` [PING][PATCH][AArch64] " Hurugalawadi, Naveen 2017-06-06 13:29 ` [PATCH][AArch64] " James Greenhalgh 0 siblings, 2 replies; 10+ messages in thread From: Hurugalawadi, Naveen @ 2017-03-10 6:37 UTC (permalink / raw) To: James Greenhalgh Cc: gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd [-- Attachment #1: Type: text/plain, Size: 336 bytes --] Hi James, >> You need to do this for all cores which might be affected by this change, >> i.e. all those which model neon_mul_d_long. Thanks for pointing out the missing cores in patch. Added the support as per your comments. Please find attached the modified patch and let us know if its okay for stage1? Thanks, Naveen [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #2: crypto_pmull-1.patch --] [-- Type: text/x-diff; name="crypto_pmull-1.patch", Size: 4135 bytes --] diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7ad3a76..1aa1b96 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5818,7 +5818,7 @@ UNSPEC_PMULL))] "TARGET_SIMD && TARGET_CRYPTO" "pmull\\t%0.1q, %1.1d, %2.1d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "aarch64_crypto_pmullv2di" @@ -5828,5 +5828,5 @@ UNSPEC_PMULL2))] "TARGET_SIMD && TARGET_CRYPTO" "pmull2\\t%0.1q, %1.2d, %2.2d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index 0dd7199..67011ac 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -441,3 +441,8 @@ (and (eq_attr "tune" "thunderx2t99") (eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q")) "thunderx2t99_ls01,thunderx2t99_f01") + +(define_insn_reservation "thunderx2t99_pmull" 5 + (and (eq_attr "tune" "thunderx2t99") + (eq_attr "type" "crypto_pmull")) + "thunderx2t99_f1") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 7cf5fc5..049ac85 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -379,7 +379,7 @@ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_q,\ neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long, neon_mla_b_q,\ + neon_sat_mul_s_scalar_long, crypto_pmull, neon_mla_b_q,\ neon_mla_h_q, neon_mla_s_q, neon_mla_b_long,\ neon_mla_h_long, neon_mla_s_long,\ neon_mla_h_scalar_q, neon_mla_s_scalar_q,\ diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index fd30758..ebf4a49 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -76,7 +76,7 @@ neon_mul_h_scalar_long, neon_mul_s_scalar_long,\ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long") + neon_sat_mul_s_scalar_long, crypto_pmull") (const_string "neon_multiply") (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\ neon_mul_h_scalar_q, neon_mul_s_scalar_q,\ diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index 46b0715..a5e558b 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -81,7 +81,7 @@ UNSPEC_VMULLP64))] "TARGET_CRYPTO" "vmull.p64\\t%q0, %P1, %P2" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "crypto_<crypto_pattern>" diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index 5d397cc..b54d4c8 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -78,7 +78,7 @@ neon_sat_mul_s_scalar, neon_sat_mul_s_scalar_q,\ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long") + neon_sat_mul_s_scalar_long, crypto_pmull") (const_string "neon_multiply") (eq_attr "type" "neon_mla_b, neon_mla_h, neon_mla_s,\ diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index b0b375c..253f496 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -539,6 +539,7 @@ ; crypto_sha1_slow ; crypto_sha256_fast ; crypto_sha256_slow +; crypto_pmull ; ; The classification below is for coprocessor instructions ; @@ -1078,6 +1079,7 @@ crypto_sha1_slow,\ crypto_sha256_fast,\ crypto_sha256_slow,\ + crypto_pmull,\ coproc" (const_string "untyped")) diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index 62a0732..34a13f4 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -527,5 +527,6 @@ (define_insn_reservation "xgene1_neon_pmull" 5 (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_mul_d_long,\ - ")) + crypto_pmull,\ + ")) "xgene1_decode2op") ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PING][PATCH][AArch64] Add crypto_pmull attribute 2017-03-10 6:37 ` Hurugalawadi, Naveen @ 2017-04-25 7:10 ` Hurugalawadi, Naveen 2017-05-11 4:52 ` [PING2][PATCH][AArch64] " Hurugalawadi, Naveen 2017-06-06 13:29 ` [PATCH][AArch64] " James Greenhalgh 1 sibling, 1 reply; 10+ messages in thread From: Hurugalawadi, Naveen @ 2017-04-25 7:10 UTC (permalink / raw) To: James Greenhalgh Cc: gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Thanks, Naveen ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PING2][PATCH][AArch64] Add crypto_pmull attribute 2017-04-25 7:10 ` [PING][PATCH][AArch64] " Hurugalawadi, Naveen @ 2017-05-11 4:52 ` Hurugalawadi, Naveen 2017-05-26 6:26 ` [PING 3][PATCH][AArch64] " Hurugalawadi, Naveen 0 siblings, 1 reply; 10+ messages in thread From: Hurugalawadi, Naveen @ 2017-05-11 4:52 UTC (permalink / raw) To: James Greenhalgh Cc: gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Thanks, Naveen ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PING 3][PATCH][AArch64] Add crypto_pmull attribute 2017-05-11 4:52 ` [PING2][PATCH][AArch64] " Hurugalawadi, Naveen @ 2017-05-26 6:26 ` Hurugalawadi, Naveen 0 siblings, 0 replies; 10+ messages in thread From: Hurugalawadi, Naveen @ 2017-05-26 6:26 UTC (permalink / raw) To: James Greenhalgh Cc: gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd Hi, Please consider this as a personal reminder to review the patch at following link and let me know your comments on the same. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Thanks, Naveen ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH][AArch64] Add crypto_pmull attribute 2017-03-10 6:37 ` Hurugalawadi, Naveen 2017-04-25 7:10 ` [PING][PATCH][AArch64] " Hurugalawadi, Naveen @ 2017-06-06 13:29 ` James Greenhalgh 2017-06-20 9:27 ` Hurugalawadi, Naveen 1 sibling, 1 reply; 10+ messages in thread From: James Greenhalgh @ 2017-06-06 13:29 UTC (permalink / raw) To: Hurugalawadi, Naveen Cc: gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd On Fri, Mar 10, 2017 at 06:37:30AM +0000, Hurugalawadi, Naveen wrote: > Hi James, > > >> You need to do this for all cores which might be affected by this change, > >> i.e. all those which model neon_mul_d_long. > > Thanks for pointing out the missing cores in patch. > Added the support as per your comments. > > Please find attached the modified patch and let us know > if its okay for stage1? From an AArch64 perspective, this is OK - but please wait for an ARM approval before you commit it. Thanks, James > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index 7ad3a76..1aa1b96 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -5818,7 +5818,7 @@ > UNSPEC_PMULL))] > "TARGET_SIMD && TARGET_CRYPTO" > "pmull\\t%0.1q, %1.1d, %2.1d" > - [(set_attr "type" "neon_mul_d_long")] > + [(set_attr "type" "crypto_pmull")] > ) > > (define_insn "aarch64_crypto_pmullv2di" > @@ -5828,5 +5828,5 @@ > UNSPEC_PMULL2))] > "TARGET_SIMD && TARGET_CRYPTO" > "pmull2\\t%0.1q, %1.2d, %2.2d" > - [(set_attr "type" "neon_mul_d_long")] > + [(set_attr "type" "crypto_pmull")] > ) > diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md > index 0dd7199..67011ac 100644 > --- a/gcc/config/aarch64/thunderx2t99.md > +++ b/gcc/config/aarch64/thunderx2t99.md > @@ -441,3 +441,8 @@ > (and (eq_attr "tune" "thunderx2t99") > (eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q")) > "thunderx2t99_ls01,thunderx2t99_f01") > + > +(define_insn_reservation "thunderx2t99_pmull" 5 > + (and (eq_attr "tune" "thunderx2t99") > + (eq_attr "type" "crypto_pmull")) > + "thunderx2t99_f1") > diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md > index 7cf5fc5..049ac85 100644 > --- a/gcc/config/arm/cortex-a53.md > +++ b/gcc/config/arm/cortex-a53.md > @@ -379,7 +379,7 @@ > neon_sat_mul_b_long, neon_sat_mul_h_long,\ > neon_sat_mul_s_long, neon_sat_mul_h_scalar_q,\ > neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ > - neon_sat_mul_s_scalar_long, neon_mla_b_q,\ > + neon_sat_mul_s_scalar_long, crypto_pmull, neon_mla_b_q,\ > neon_mla_h_q, neon_mla_s_q, neon_mla_b_long,\ > neon_mla_h_long, neon_mla_s_long,\ > neon_mla_h_scalar_q, neon_mla_s_scalar_q,\ > diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md > index fd30758..ebf4a49 100644 > --- a/gcc/config/arm/cortex-a57.md > +++ b/gcc/config/arm/cortex-a57.md > @@ -76,7 +76,7 @@ > neon_mul_h_scalar_long, neon_mul_s_scalar_long,\ > neon_sat_mul_b_long, neon_sat_mul_h_long,\ > neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ > - neon_sat_mul_s_scalar_long") > + neon_sat_mul_s_scalar_long, crypto_pmull") > (const_string "neon_multiply") > (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\ > neon_mul_h_scalar_q, neon_mul_s_scalar_q,\ > diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md > index 46b0715..a5e558b 100644 > --- a/gcc/config/arm/crypto.md > +++ b/gcc/config/arm/crypto.md > @@ -81,7 +81,7 @@ > UNSPEC_VMULLP64))] > "TARGET_CRYPTO" > "vmull.p64\\t%q0, %P1, %P2" > - [(set_attr "type" "neon_mul_d_long")] > + [(set_attr "type" "crypto_pmull")] > ) > > (define_insn "crypto_<crypto_pattern>" > diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md > index 5d397cc..b54d4c8 100644 > --- a/gcc/config/arm/exynos-m1.md > +++ b/gcc/config/arm/exynos-m1.md > @@ -78,7 +78,7 @@ > neon_sat_mul_s_scalar, neon_sat_mul_s_scalar_q,\ > neon_sat_mul_b_long, neon_sat_mul_h_long,\ > neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ > - neon_sat_mul_s_scalar_long") > + neon_sat_mul_s_scalar_long, crypto_pmull") > (const_string "neon_multiply") > > (eq_attr "type" "neon_mla_b, neon_mla_h, neon_mla_s,\ > diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md > index b0b375c..253f496 100644 > --- a/gcc/config/arm/types.md > +++ b/gcc/config/arm/types.md > @@ -539,6 +539,7 @@ > ; crypto_sha1_slow > ; crypto_sha256_fast > ; crypto_sha256_slow > +; crypto_pmull > ; > ; The classification below is for coprocessor instructions > ; > @@ -1078,6 +1079,7 @@ > crypto_sha1_slow,\ > crypto_sha256_fast,\ > crypto_sha256_slow,\ > + crypto_pmull,\ > coproc" > (const_string "untyped")) > > diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md > index 62a0732..34a13f4 100644 > --- a/gcc/config/arm/xgene1.md > +++ b/gcc/config/arm/xgene1.md > @@ -527,5 +527,6 @@ > (define_insn_reservation "xgene1_neon_pmull" 5 > (and (eq_attr "tune" "xgene1") > (eq_attr "type" "neon_mul_d_long,\ > - ")) > + crypto_pmull,\ > + ")) > "xgene1_decode2op") ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH][AArch64] Add crypto_pmull attribute 2017-06-06 13:29 ` [PATCH][AArch64] " James Greenhalgh @ 2017-06-20 9:27 ` Hurugalawadi, Naveen 2017-06-20 9:41 ` Ramana Radhakrishnan 0 siblings, 1 reply; 10+ messages in thread From: Hurugalawadi, Naveen @ 2017-06-20 9:27 UTC (permalink / raw) To: James Greenhalgh Cc: gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd Hi James, Thanks for the approval. >> From an AArch64 perspective, this is OK - but please wait for an ARM >> approval before you commit it. Can anyone from ARM comment on the patch so that it can be committed upstream if no issues. https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Thanks, Naveen ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH][AArch64] Add crypto_pmull attribute 2017-06-20 9:27 ` Hurugalawadi, Naveen @ 2017-06-20 9:41 ` Ramana Radhakrishnan 2017-06-21 5:55 ` Hurugalawadi, Naveen 0 siblings, 1 reply; 10+ messages in thread From: Ramana Radhakrishnan @ 2017-06-20 9:41 UTC (permalink / raw) To: Hurugalawadi, Naveen Cc: James Greenhalgh, gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd On Tue, Jun 20, 2017 at 10:26 AM, Hurugalawadi, Naveen <Naveen.Hurugalawadi@cavium.com> wrote: > Hi James, > > Thanks for the approval. > >>> From an AArch64 perspective, this is OK - but please wait for an ARM >>> approval before you commit it. > > Can anyone from ARM comment on the patch so that it can be committed > upstream if no issues. > > https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html Please update the ARM backend with the new attribute too .... crypto.md: (define_insn "crypto_vmullp64" [(set (match_operand:TI 0 "register_operand" "=w") (unspec:TI [(match_operand:DI 1 "register_operand" "w") (match_operand:DI 2 "register_operand" "w")] UNSPEC_VMULLP64))] "TARGET_CRYPTO" "vmull.p64\\t%q0, %P1, %P2" [(set_attr "type" "neon_mul_d_long")] ) Ok with that change and checking that you can build cc1 for arm-none-eabi . regards Ramana > > Thanks, > Naveen > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH][AArch64] Add crypto_pmull attribute 2017-06-20 9:41 ` Ramana Radhakrishnan @ 2017-06-21 5:55 ` Hurugalawadi, Naveen 0 siblings, 0 replies; 10+ messages in thread From: Hurugalawadi, Naveen @ 2017-06-21 5:55 UTC (permalink / raw) To: Ramana Radhakrishnan Cc: James Greenhalgh, gcc-patches, Pinski, Andrew, Marcus Shawcroft, Richard Earnshaw, nd Hi Ramana, Thanks for the review and approval. >> Please update the ARM backend with the new attribute too >> (define_insn "crypto_vmullp64" Its already been updated in the patch posted at:- https://gcc.gnu.org/ml/gcc-patches/2017-03/msg00504.html >> Ok with that change and checking that you can build cc1 for arm-none-eabi . Checked and built the arm toolchain successfully with the patch. Patch has been committed at:- https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=249433 Thanks, Naveen ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-06-21 5:55 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-03-06 5:11 [PATCH][AArch64] Add crypto_pmull attribute Hurugalawadi, Naveen 2017-03-09 10:51 ` James Greenhalgh 2017-03-10 6:37 ` Hurugalawadi, Naveen 2017-04-25 7:10 ` [PING][PATCH][AArch64] " Hurugalawadi, Naveen 2017-05-11 4:52 ` [PING2][PATCH][AArch64] " Hurugalawadi, Naveen 2017-05-26 6:26 ` [PING 3][PATCH][AArch64] " Hurugalawadi, Naveen 2017-06-06 13:29 ` [PATCH][AArch64] " James Greenhalgh 2017-06-20 9:27 ` Hurugalawadi, Naveen 2017-06-20 9:41 ` Ramana Radhakrishnan 2017-06-21 5:55 ` Hurugalawadi, Naveen
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