From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 47492 invoked by alias); 16 Jun 2017 19:52:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 47481 invoked by uid 89); 16 Jun 2017 19:52:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Hx-languages-length:1793, super X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 Jun 2017 19:52:52 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v5GJqm6G018620; Fri, 16 Jun 2017 14:52:49 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id v5GJqlZx018614; Fri, 16 Jun 2017 14:52:47 -0500 Date: Fri, 16 Jun 2017 19:52:00 -0000 From: Segher Boessenkool To: Michael Meissner , GCC Patches , David Edelsohn , Bill Schmidt Subject: Re: [PATCH, rev 2] PR target/79799, Add vec_insert of V4SFmode on PowerPC ISA 3.0 (power9) Message-ID: <20170616195246.GH16550@gate.crashing.org> References: <20170615000158.GA11033@ibm-tiger.the-meissners.org> <20170615233938.GA15195@ibm-tiger.the-meissners.org> <20170616021027.GA2916@ibm-tiger.the-meissners.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170616021027.GA2916@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg01233.txt.bz2 Hi Mike, On Thu, Jun 15, 2017 at 10:10:28PM -0400, Michael Meissner wrote: > +(define_insn_and_split "vsx_set_v4sf_p9" > + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa") > + (unspec:V4SF > + [(match_operand:V4SF 1 "gpc_reg_operand" "0") > + (match_operand:SF 2 "gpc_reg_operand" "ww") > + (match_operand:QI 3 "const_0_to_3_operand" "n")] > + UNSPEC_VSX_SET)) > + (clobber (match_scratch:SI 4 "=&wJwK"))] > + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR" > + "#" > + "&& reload_completed" I still don't think it is such a good idea to do all of this not until after reload. It does of course allow you to play tricks with changing register mode at will, like you do ;-) All these unspecs are a similar problem: the RTL optimisers cannot do much at all with it. > + [(set_attr "type" "vecperm") Is that a good type for this? I think the convert is more expensive than the permutes? If so, that would be better (of course it only matters for sched1, not super important). > --- gcc/testsuite/gcc.target/powerpc/pr79799-1.c (nonexistent) > +++ gcc/testsuite/gcc.target/powerpc/pr79799-1.c (working copy) > @@ -0,0 +1,43 @@ > +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ Why not powerpc*-*-*? > +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-options "-mcpu=power9 -O2" } */ > + > +#include > + > +/* GCC 7.1 did not have a specialized method for inserting 32-bit floating point on > + ISA 3.0 (power9) systems. */ That first line is a bit long. The patch is okay for trunk and 7 with the testsuite nits taken care of. Thanks, Segher