From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 55071 invoked by alias); 16 Jun 2017 20:27:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 55062 invoked by uid 89); 16 Jun 2017 20:27:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,KHOP_DYNAMIC,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 Jun 2017 20:27:00 +0000 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v5GKNhWH082855 for ; Fri, 16 Jun 2017 16:27:03 -0400 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0a-001b2d01.pphosted.com with ESMTP id 2b4np49b7e-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 16 Jun 2017 16:27:03 -0400 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 16 Jun 2017 16:26:59 -0400 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v5GKQxMP62980316; Fri, 16 Jun 2017 20:26:59 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9FC68AE03B; Fri, 16 Jun 2017 16:26:57 -0400 (EDT) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 850FDAE034; Fri, 16 Jun 2017 16:26:57 -0400 (EDT) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 7978F4756A; Fri, 16 Jun 2017 16:26:58 -0400 (EDT) Date: Fri, 16 Jun 2017 20:27:00 -0000 From: Michael Meissner To: Segher Boessenkool Cc: Michael Meissner , GCC Patches , David Edelsohn , Bill Schmidt Subject: Re: [PATCH, rev 2] PR target/79799, Add vec_insert of V4SFmode on PowerPC ISA 3.0 (power9) Mail-Followup-To: Michael Meissner , Segher Boessenkool , GCC Patches , David Edelsohn , Bill Schmidt References: <20170615000158.GA11033@ibm-tiger.the-meissners.org> <20170615233938.GA15195@ibm-tiger.the-meissners.org> <20170616021027.GA2916@ibm-tiger.the-meissners.org> <20170616195246.GH16550@gate.crashing.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170616195246.GH16550@gate.crashing.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 x-cbid: 17061620-0024-0000-0000-000002959A55 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007244; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000214; SDB=6.00875761; UDB=6.00436065; IPR=6.00655849; BA=6.00005425; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015856; XFM=3.00000015; UTC=2017-06-16 20:27:01 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17061620-0025-0000-0000-00004469D016 Message-Id: <20170616202658.GA2150@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-16_11:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706160343 X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg01235.txt.bz2 On Fri, Jun 16, 2017 at 02:52:46PM -0500, Segher Boessenkool wrote: > Hi Mike, > > On Thu, Jun 15, 2017 at 10:10:28PM -0400, Michael Meissner wrote: > > +(define_insn_and_split "vsx_set_v4sf_p9" > > + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa") > > + (unspec:V4SF > > + [(match_operand:V4SF 1 "gpc_reg_operand" "0") > > + (match_operand:SF 2 "gpc_reg_operand" "ww") > > + (match_operand:QI 3 "const_0_to_3_operand" "n")] > > + UNSPEC_VSX_SET)) > > + (clobber (match_scratch:SI 4 "=&wJwK"))] > > + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR" > > + "#" > > + "&& reload_completed" > > I still don't think it is such a good idea to do all of this not until > after reload. It does of course allow you to play tricks with changing > register mode at will, like you do ;-) The problem is MODES_TIEABLE_P. V4S{I,F}mode and SImode cannot be tied together (i.e. use gen_lowpart to change the mode and use a SUBREG). So after reload, we can just use gen_rtx_REG (...) to change the register type, but before reload, by creating the SUBREG, it can lead to various aborts if rtl checking is turned on. > All these unspecs are a similar problem: the RTL optimisers cannot do > much at all with it. I don't think there is a good way to represent a vec_insert. And vec_extract can't represent a variable extract either. > > + [(set_attr "type" "vecperm") I generally use the type of the last insn. I am open to other suggestions. > Is that a good type for this? I think the convert is more expensive > than the permutes? If so, that would be better (of course it only > matters for sched1, not super important). > > > --- gcc/testsuite/gcc.target/powerpc/pr79799-1.c (nonexistent) > > +++ gcc/testsuite/gcc.target/powerpc/pr79799-1.c (working copy) > > @@ -0,0 +1,43 @@ > > +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ > > Why not powerpc*-*-*? Well as it turns out, it aborts in 32-bit, because -mvsx-small-integer is not enabled, and we can't have SImode in vector registers. I'll have to add some additional tests and resubmit the patch. > > > +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ > > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > > +/* { dg-options "-mcpu=power9 -O2" } */ > > + > > +#include > > + > > +/* GCC 7.1 did not have a specialized method for inserting 32-bit floating point on > > + ISA 3.0 (power9) systems. */ > > That first line is a bit long. Ok. > The patch is okay for trunk and 7 with the testsuite nits taken care of. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797