* [PATCH] Fix x86 ICE with -mtune=amdfam10 -mno-sse2 (PR target/81121)
@ 2017-06-19 15:37 Jakub Jelinek
2017-06-20 5:52 ` Uros Bizjak
0 siblings, 1 reply; 2+ messages in thread
From: Jakub Jelinek @ 2017-06-19 15:37 UTC (permalink / raw)
To: Uros Bizjak; +Cc: gcc-patches
Hi!
This testcase started to ICE when PR70873 fix changed the splitter:
@@ -5153,11 +5147,11 @@
;; slots when !TARGET_INTER_UNIT_MOVES_TO_VEC disables the general_regs
;; alternative in sse2_loadld.
(define_split
- [(set (match_operand:MODEF 0 "register_operand")
+ [(set (match_operand:MODEF 0 "sse_reg_operand")
(float:MODEF (match_operand:SI 1 "nonimmediate_operand")))]
- "TARGET_SSE2 && TARGET_SSE_MATH
- && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
- && reload_completed && SSE_REG_P (operands[0])
+ "TARGET_USE_VECTOR_CONVERTS
+ && optimize_function_for_speed_p (cfun)
+ && reload_completed
&& (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
&& (!EXT_REX_SSE_REG_P (operands[0])
|| TARGET_AVX512VL)"
Having sse_reg_operand match the output operand does not imply
TARGET_SSE2 is enabled, but we need it for both the
if (<ssevecmode>mode == V4SFmode)
emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
else
emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
instructions that we want to use in the splitter.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk
(or do you want TARGET_SSE2 first or right after
TARGET_USE_VECTOR_CONVERTS)?
2017-06-19 Jakub Jelinek <jakub@redhat.com>
PR target/81121
* config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df}
splitter): Require TARGET_SSE2 in the condition.
* gcc.target/i386/pr81121.c: New test.
--- gcc/config/i386/i386.md.jj 2017-06-08 20:50:46.000000000 +0200
+++ gcc/config/i386/i386.md 2017-06-19 11:30:38.937491668 +0200
@@ -5294,6 +5294,7 @@ (define_split
&& optimize_function_for_speed_p (cfun)
&& reload_completed
&& (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
+ && TARGET_SSE2
&& (!EXT_REX_SSE_REG_P (operands[0])
|| TARGET_AVX512VL)"
[(const_int 0)]
--- gcc/testsuite/gcc.target/i386/pr81121.c.jj 2017-06-19 11:36:06.545501324 +0200
+++ gcc/testsuite/gcc.target/i386/pr81121.c 2017-06-19 11:35:40.000000000 +0200
@@ -0,0 +1,10 @@
+/* PR target/81121 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=amdfam10 -mno-sse2" } */
+
+void
+foo (short *x, short *y)
+{
+ float a = 0;
+ y[0] = x[0] * a;
+}
Jakub
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] Fix x86 ICE with -mtune=amdfam10 -mno-sse2 (PR target/81121)
2017-06-19 15:37 [PATCH] Fix x86 ICE with -mtune=amdfam10 -mno-sse2 (PR target/81121) Jakub Jelinek
@ 2017-06-20 5:52 ` Uros Bizjak
0 siblings, 0 replies; 2+ messages in thread
From: Uros Bizjak @ 2017-06-20 5:52 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: gcc-patches
On Mon, Jun 19, 2017 at 5:37 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> Hi!
>
> This testcase started to ICE when PR70873 fix changed the splitter:
> @@ -5153,11 +5147,11 @@
> ;; slots when !TARGET_INTER_UNIT_MOVES_TO_VEC disables the general_regs
> ;; alternative in sse2_loadld.
> (define_split
> - [(set (match_operand:MODEF 0 "register_operand")
> + [(set (match_operand:MODEF 0 "sse_reg_operand")
> (float:MODEF (match_operand:SI 1 "nonimmediate_operand")))]
> - "TARGET_SSE2 && TARGET_SSE_MATH
> - && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
> - && reload_completed && SSE_REG_P (operands[0])
> + "TARGET_USE_VECTOR_CONVERTS
> + && optimize_function_for_speed_p (cfun)
> + && reload_completed
> && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
> && (!EXT_REX_SSE_REG_P (operands[0])
> || TARGET_AVX512VL)"
> Having sse_reg_operand match the output operand does not imply
> TARGET_SSE2 is enabled, but we need it for both the
> if (<ssevecmode>mode == V4SFmode)
> emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4]));
> else
> emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4]));
> instructions that we want to use in the splitter.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk
> (or do you want TARGET_SSE2 first or right after
> TARGET_USE_VECTOR_CONVERTS)?
Please put TARGET_SSE2 first in the insn condition.
> 2017-06-19 Jakub Jelinek <jakub@redhat.com>
>
> PR target/81121
> * config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df}
> splitter): Require TARGET_SSE2 in the condition.
>
> * gcc.target/i386/pr81121.c: New test.
OK with the above change.
Thanks,
Uros.
> --- gcc/config/i386/i386.md.jj 2017-06-08 20:50:46.000000000 +0200
> +++ gcc/config/i386/i386.md 2017-06-19 11:30:38.937491668 +0200
> @@ -5294,6 +5294,7 @@ (define_split
> && optimize_function_for_speed_p (cfun)
> && reload_completed
> && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
> + && TARGET_SSE2
> && (!EXT_REX_SSE_REG_P (operands[0])
> || TARGET_AVX512VL)"
> [(const_int 0)]
> --- gcc/testsuite/gcc.target/i386/pr81121.c.jj 2017-06-19 11:36:06.545501324 +0200
> +++ gcc/testsuite/gcc.target/i386/pr81121.c 2017-06-19 11:35:40.000000000 +0200
> @@ -0,0 +1,10 @@
> +/* PR target/81121 */
> +/* { dg-do compile } */
> +/* { dg-options "-O0 -march=amdfam10 -mno-sse2" } */
> +
> +void
> +foo (short *x, short *y)
> +{
> + float a = 0;
> + y[0] = x[0] * a;
> +}
>
> Jakub
^ permalink raw reply [flat|nested] 2+ messages in thread
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2017-06-19 15:37 [PATCH] Fix x86 ICE with -mtune=amdfam10 -mno-sse2 (PR target/81121) Jakub Jelinek
2017-06-20 5:52 ` Uros Bizjak
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