From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 49190 invoked by alias); 19 Jun 2017 22:43:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 49173 invoked by uid 89); 19 Jun 2017 22:43:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Love, love X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 19 Jun 2017 22:43:44 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v5JMhk1w027512; Mon, 19 Jun 2017 17:43:47 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id v5JMhjnf027511; Mon, 19 Jun 2017 17:43:45 -0500 Date: Mon, 19 Jun 2017 22:43:00 -0000 From: Segher Boessenkool To: Carl Love Cc: gcc-patches@gcc.gnu.org, David Edelsohn , Bill Schmidt Subject: Re: [PATCH, rs6000] Fix vec_mulo and vec_mule instruction generation Message-ID: <20170619224345.GO16550@gate.crashing.org> References: <1497647945.3664.36.camel@us.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1497647945.3664.36.camel@us.ibm.com> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg01387.txt.bz2 Hi Carl, On Fri, Jun 16, 2017 at 02:19:05PM -0700, Carl Love wrote: > * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add Indent is broken on this line. > ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW, > ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW enties. Typo ("entries"). > * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin(), > builtin_function_type()): Add needed ALTIVEC_BUILTIN_* case > statements. No () please, just the names. > * config/rs6000/altivec.md (define_c_enum "unspec", > define_expand "vec_widen_umult_even_v4si", > define_expand "vec_widen_smult_even_v4si", > define_expand "vec_widen_umult_odd_v4si", > define_expand "vec_widen_smult_odd_v4si", > define_insn "altivec_vmuleuw", define_insn "altivec_vmulesw", > define_insn "altivec_vmulouw", define_insn "altivec_vmulosw"): Add > support to generate vmuleuw, vmulesw, vmulouw, vmulosw instructions. (UNSPEC_VMULEUW, UNSPEC_VMULESW, UNSPEC_VMULOUW, UNSPEC_VMULOSW): New enum "unspec" values. (vec_widen_umult_even_v4si, vec_widen_smult_even_v4si, vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si, altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw, altivec_vmulosw): New patterns. (Or similar. Mention all new names added. Usually for new things, just saying "New." or "New frobnitz." is enough; the changelog does not describe the design, or why you added something: it says just what changed). > +(define_expand "vec_widen_umult_even_v4si" > + [(use (match_operand:V2DI 0 "register_operand" "")) > + (use (match_operand:V4SI 1 "register_operand" "")) > + (use (match_operand:V4SI 2 "register_operand" ""))] You can leave off the default (empty) constraint strings, in expanders. > + "TARGET_ALTIVEC" > +{ > + if (VECTOR_ELT_ORDER_BIG) > + emit_insn (gen_altivec_vmuleuw (operands[0], operands[1], > operands[2])); Your patch was wrapped in the mail. Please try to prevent that, so that other people can apply the patch to test out, etc. > +(define_insn "altivec_vmuleuw" > + [(set (match_operand:V2DI 0 "register_operand" "=v") > + (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v") > + (match_operand:V4SI 2 "register_operand" "v")] > + UNSPEC_VMULEUW))] The one-but-last line should be indented with tabs instead of spaces, too. (This happens a few time more later in the patch; please check it all). Okay for trunk with those last nits fixed. Thanks! Segher