From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 97340 invoked by alias); 20 Jun 2017 20:06:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 97278 invoked by uid 89); 20 Jun 2017 20:06:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.0 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=H*r:8.14.5, UD:netbsd.org, our X-HELO: mx.sdf.org Received: from mx.sdf.org (HELO mx.sdf.org) (205.166.94.20) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Jun 2017 20:06:05 +0000 Received: from sdf.org (IDENT:coypu@sdf.lonestar.org [205.166.94.15]) by mx.sdf.org (8.15.2/8.14.5) with ESMTPS id v5KK5i0W015795 (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256 bits) verified NO); Tue, 20 Jun 2017 20:05:44 GMT Received: (from coypu@localhost) by sdf.org (8.15.2/8.12.8/Submit) id v5KK5g3U013514; Tue, 20 Jun 2017 20:05:42 GMT Date: Tue, 20 Jun 2017 20:06:00 -0000 From: coypu@sdf.org To: gcc-patches@gcc.gnu.org Cc: matt@3am-software.com, m4j0rd0m0@gmail.com, paulkoning@comcast.net, jbglaw@lug-owl.de Subject: [PATCH, VAX] Correct ffs instruction constraint Message-ID: <20170620200542.GA17979@SDF.ORG> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.8.0 (2017-02-23) X-IsSubscribed: yes X-SW-Source: 2017-06/txt/msg01508.txt.bz2 VAX' FFS as variable-length bit field instruction uses a "base" operand of type "vb" meaning "byte address". "base" can be 32 bits (SI) and due to the definition of ffssi2/__builtin_ffs() with the operand constraint "m", code can be emitted which incorrectly implies a mode-dependent (= longword, for the 32-bit operand) address. File scsipi_base.c compiled with -Os for our VAX install kernel shows: ffs $0x0,$0x20,0x50(r11)[r0],r9 Apparently, 0x50(r11)[r0] as a longword address is assumed to be evaluated in longword context by FFS, but the instruction expects a byte address. Our fix is to change the operand constraint from "m" to "Q", i. e. "operand is a MEM that does not have a mode-dependent address", which results in: moval 0x50(r11)[r0],r1 ffs $0x0,$0x20,(r1),r9 MOVAL evaluates the source operand/address in longword context, so effectively converts the word address to a byte address for FFS. See NetBSD PR port-vax/51761 (http://gnats.netbsd.org/51761) and discussion on port-vax mailing list (http://mail-index.netbsd.org/port-vax/2017/01/06/msg002954.html). Changlog: 2017-06-20 Maya Rashish * gcc/config/vax/builtins.md: Correct ffssi2_internal instruction constraint. --- gcc/config/vax/builtins.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/vax/builtins.md b/gcc/config/vax/builtins.md index fb0f69acb..b78fb5616 100644 --- a/gcc/config/vax/builtins.md +++ b/gcc/config/vax/builtins.md @@ -41,7 +41,7 @@ (define_insn "ffssi2_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=rQ") - (ffs:SI (match_operand:SI 1 "general_operand" "nrmT"))) + (ffs:SI (match_operand:SI 1 "general_operand" "nrQT"))) (set (cc0) (match_dup 0))] "" "ffs $0,$32,%1,%0") -- 2.13.1