[PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Daniel Cederman]

This patch adds a workaround to the Sparc backend for the LEON3FT
store-store errata. It is enabled when using the -mfix-ut699,
-mfix-ut700, or -mfix-gr712rc flag.

The workaround inserts NOP instructions to prevent the following two
instruction sequences from being generated:

std -> stb/sth/st/std
stb/sth/st -> any single non-store/load instruction -> stb/sth/st/std

The __FIX_B2BST define can be used to only enable workarounds in assembly
code when the flag is used.

See GRLIB-TN-0009, "LEON3FT Stale Cache Entry After Store with Data Tag
Parity Error", for more information.

gcc/ChangeLog:

2017-06-21  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
	instructions to prevent sequences that can trigger the store-store
	errata for certain LEON3FT processors.
	(sparc_option_override): -mfix-ut699, -mfix-ut700, and
	-mfix-gr712rc enables the errata workaround.
	* config/sparc/sparc-c.c (sparc_target_macros): Define __FIX_B2BST
	when errata workaround is enabled.
	* config/sparc/sparc.md: Prevent stores in delay slot.
	* config/sparc/sparc.opt: Add -mfix-ut700 and -mfix-gr712rc flag.
	* doc/invoke.texi: Document -mfix-ut700 and -mfix-gr712rc flag.
---
 gcc/config/sparc/sparc-c.c |  3 ++
 gcc/config/sparc/sparc.c   | 98 +++++++++++++++++++++++++++++++++++++++++++++-
 gcc/config/sparc/sparc.md  | 10 ++++-
 gcc/config/sparc/sparc.opt | 12 ++++++
 gcc/doc/invoke.texi        | 14 ++++++-
 5 files changed, 131 insertions(+), 6 deletions(-)

diff --git a/gcc/config/sparc/sparc-c.c b/gcc/config/sparc/sparc-c.c
index 9603173..6979f9c 100644
--- a/gcc/config/sparc/sparc-c.c
+++ b/gcc/config/sparc/sparc-c.c
@@ -60,4 +60,7 @@ sparc_target_macros (void)
       cpp_define (parse_in, "__VIS__=0x100");
       cpp_define (parse_in, "__VIS=0x100");
     }
+
+  if (sparc_fix_b2bst)
+    builtin_define_std ("__FIX_B2BST");
 }
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 790a036..ebf2eda 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -896,6 +896,12 @@ mem_ref (rtx x)
    to properly detect the various hazards.  Therefore, this machine specific
    pass runs as late as possible.  */
 
+/* True if INSN is a md pattern or asm statement.  */
+#define USEFUL_INSN_P(INSN)						\
+  (NONDEBUG_INSN_P (INSN)						\
+   && GET_CODE (PATTERN (INSN)) != USE					\
+   && GET_CODE (PATTERN (INSN)) != CLOBBER)
+
 static unsigned int
 sparc_do_work_around_errata (void)
 {
@@ -915,6 +921,81 @@ sparc_do_work_around_errata (void)
 	if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
 	  insn = seq->insn (1);
 
+      /* Look for either of these two sequences:
+
+	 Sequence A:
+	 1. store of word size or less (e.g. st / stb / sth / stf)
+	 2. any single instruction that is not a load or store
+	 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
+
+	 Sequence B:
+	 1. store of double word size (e.g. std / stdf)
+	 2. any store instruction (e.g. st / stb / sth / stf / std / stdf)  */
+      if (sparc_fix_b2bst
+	  && NONJUMP_INSN_P (insn)
+	  && (set = single_set (insn)) != NULL_RTX
+	  && MEM_P (SET_DEST (set)))
+	{
+	  /* Sequence B begins with a double-word store.  */
+	  bool seq_b = GET_MODE_SIZE (GET_MODE (SET_DEST (set))) == 8;
+	  rtx_insn *after;
+	  int i;
+
+	  next = next_active_insn (insn);
+	  if (!next)
+	    break;
+
+	  for (after = next, i = 0; i < 2; i++)
+	    {
+	      /* Skip empty assembly statements.  */
+	      if ((GET_CODE (PATTERN (after)) == UNSPEC_VOLATILE)
+		  || (USEFUL_INSN_P (after)
+		      && (asm_noperands (PATTERN (after))>=0)
+		      && !strcmp (decode_asm_operands (PATTERN (after),
+						       NULL, NULL, NULL,
+						       NULL, NULL), "")))
+		after = next_active_insn (after);
+	      if (!after)
+		break;
+
+	      /* If the insn is a branch, then it cannot be problematic.  */
+	      if (!NONJUMP_INSN_P (after)
+		  || GET_CODE (PATTERN (after)) == SEQUENCE)
+		break;
+
+	      /* Sequence B is only two instructions long.  */
+	      if (seq_b)
+		{
+		  /* Add NOP if followed by a store.  */
+		  if ((set = single_set (after)) != NULL_RTX
+		      && MEM_P (SET_DEST (set)))
+		    insert_nop = true;
+
+		  /* Otherwise it is ok.  */
+		  break;
+		}
+
+	      /* If the second instruction is a load or a store,
+		 then the sequence cannot be problematic.  */
+	      if (i == 0)
+		{
+		  if (((set = single_set (after)) != NULL_RTX)
+		      && (MEM_P (SET_DEST (set)) || MEM_P (SET_SRC (set))))
+		    break;
+
+		  after = next_active_insn (after);
+		  if (!after)
+		    break;
+		}
+
+	      /* Add NOP if third instruction is a store.  */
+	      if (i == 1
+		  && ((set = single_set (after)) != NULL_RTX)
+		  && MEM_P (SET_DEST (set)))
+		insert_nop = true;
+	    }
+	}
+      else
       /* Look for a single-word load into an odd-numbered FP register.  */
       if (sparc_fix_at697f
 	  && NONJUMP_INSN_P (insn)
@@ -1167,8 +1248,9 @@ public:
   /* opt_pass methods: */
   virtual bool gate (function *)
     {
-      /* The only errata we handle are those of the AT697F and UT699.  */
-      return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
+      /* The only errata we handle are those of the AT697F,
+	 UT699, and certain LEON3FT.  */
+      return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst;
     }
 
   virtual unsigned int execute (function *)
@@ -1519,6 +1601,18 @@ sparc_option_override (void)
   if (!(target_flags_explicit & MASK_LRA))
     target_flags |= MASK_LRA;
 
+  /* -mfix-ut699 enables the back-to-back store errata workaround.  */
+  if (sparc_fix_ut699)
+    sparc_fix_b2bst = 1;
+
+  /* -mfix-ut700 enables the back-to-back store errata workaround.  */
+  if (sparc_fix_ut700)
+    sparc_fix_b2bst = 1;
+
+  /* -mfix-gr712rc enables the back-to-back store errata workaround.  */
+  if (sparc_fix_gr712rc)
+    sparc_fix_b2bst = 1;
+
   /* Supply a default value for align_functions.  */
   if (align_functions == 0)
     {
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 5c5096b..6c1b1e3 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -329,6 +329,10 @@
    (symbol_ref "(sparc_fix_ut699 != 0
 		 ? FIX_UT699_TRUE : FIX_UT699_FALSE)"))
 
+(define_attr "fix_b2bst" "false,true"
+   (symbol_ref "(sparc_fix_b2bst != 0
+		 ? FIX_B2BST_TRUE : FIX_B2BST_FALSE)"))
+
 ;; Length (in # of insns).
 ;; Beware that setting a length greater or equal to 3 for conditional branches
 ;; has a side-effect (see output_cbranch and output_v9branch).
@@ -476,6 +480,8 @@
 (define_attr "in_branch_delay" "false,true"
   (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
 	   (const_string "false")
+	 (and (eq_attr "fix_b2bst" "true") (eq_attr "type" "store,fpstore"))
+	   (const_string "false")
 	 (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))
 	   (const_string "false")
 	 (and (eq_attr "fix_ut699" "true")
@@ -6061,7 +6067,7 @@
 	(div:DF (match_operand:DF 1 "register_operand" "e")
 		(match_operand:DF 2 "register_operand" "e")))]
   "TARGET_FPU && sparc_fix_ut699"
-  "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"
+  "fdivd\t%1, %2, %0\n\tnop\n\tstd\t%0, [%%sp-8]\n\tnop"
   [(set_attr "type" "fpdivd")
    (set_attr "fptype" "double")
    (set_attr "length" "2")])
@@ -6313,7 +6319,7 @@
   [(set (match_operand:DF 0 "register_operand" "=e")
 	(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
   "TARGET_FPU && sparc_fix_ut699"
-  "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"
+  "fsqrtd\t%1, %0\n\tnop\n\tstd\t%0, [%%sp-8]\n\tnop"
   [(set_attr "type" "fpsqrtd")
    (set_attr "fptype" "double")
    (set_attr "length" "2")])
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 86f85d9..a44945f 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -230,6 +230,18 @@ mfix-ut699
 Target Report RejectNegative Var(sparc_fix_ut699)
 Enable workarounds for the errata of the UT699 processor.
 
+mfix-ut700
+Target Report RejectNegative Var(sparc_fix_ut700)
+Enable workarounds for the errata of the UT699E/UT700 processor.
+
+mfix-gr712rc
+Target Report RejectNegative Var(sparc_fix_gr712rc)
+Enable workarounds for the errata of the GR712RC processor.
+
+;; Enable workaround for back-to-back store errata
+TargetVariable
+unsigned int sparc_fix_b2bst
+
 Mask(LONG_DOUBLE_128)
 ;; Use 128-bit long double
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d1e097b..c66e409 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1127,8 +1127,8 @@ See RS/6000 and PowerPC Options.
 -mvis2  -mno-vis2  -mvis3  -mno-vis3 @gol
 -mcbcond  -mno-cbcond  -mfmaf  -mno-fmaf  @gol
 -mpopc  -mno-popc  -msubxc  -mno-subxc@gol
--mfix-at697f  -mfix-ut699 @gol
--mlra  -mno-lra}
+-mfix-at697f  -mfix-ut699 -mfix-ut700 @gol
+-mfix-gr712rc -mlra  -mno-lra}
 
 @emph{SPU Options}
 @gccoptlist{-mwarn-reloc  -merror-reloc @gol
@@ -24043,6 +24043,16 @@ processor (which corresponds to erratum #13 of the AT697E processor).
 @opindex mfix-ut699
 Enable the documented workarounds for the floating-point errata and the data
 cache nullify errata of the UT699 processor.
+
+@item -mfix-ut700
+@opindex mfix-ut700
+Enable the documented workaround for the back-to-back store errata of
+the UT699E/UT700 processor.
+
+@item -mfix-gr712rc
+@opindex mfix-gr712rc
+Enable the documented workaround for the back-to-back store errata of
+the GR712RC processor.
 @end table
 
 These @samp{-m} options are supported in addition to the above
-- 
2.9.3

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Eric Botcazou]

> This patch adds a workaround to the Sparc backend for the LEON3FT
> store-store errata. It is enabled when using the -mfix-ut699,
> -mfix-ut700, or -mfix-gr712rc flag.

Let's forget -mfix-gr712rc for now, -mfix-ut700 is enough I think.

> The workaround inserts NOP instructions to prevent the following two
> instruction sequences from being generated:
> 
> std -> stb/sth/st/std
> stb/sth/st -> any single non-store/load instruction -> stb/sth/st/std
> 
> The __FIX_B2BST define can be used to only enable workarounds in assembly
> code when the flag is used.

I'm not thrilled with this, it's undocumented, the other workaround don't have 
it and I don't think that we really need it.

> See GRLIB-TN-0009, "LEON3FT Stale Cache Entry After Store with Data Tag
> Parity Error", for more information.
> 
> gcc/ChangeLog:
> 
> 2017-06-21  Daniel Cederman  <cederman@gaisler.com>
> 
> 	* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
> 	instructions to prevent sequences that can trigger the store-store
> 	errata for certain LEON3FT processors.
> 	(sparc_option_override): -mfix-ut699, -mfix-ut700, and
> 	-mfix-gr712rc enables the errata workaround.
> 	* config/sparc/sparc-c.c (sparc_target_macros): Define __FIX_B2BST
> 	when errata workaround is enabled.
> 	* config/sparc/sparc.md: Prevent stores in delay slot.
> 	* config/sparc/sparc.opt: Add -mfix-ut700 and -mfix-gr712rc flag.
> 	* doc/invoke.texi: Document -mfix-ut700 and -mfix-gr712rc flag.

OK for mainline and 7 branch modulo the above two remarks.

-- 
Eric Botcazou

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Daniel Cederman]

Hello Eric,

Thank you for reviewing the patch.

> Let's forget -mfix-gr712rc for now, -mfix-ut700 is enough I think.

I think it would be confusing to use the -mfix-ut700 flag when compiling 
for the GR712RC. Now when we are not using a generic name for the errata 
workaround we should at least have unique flags for the two major CPUs 
that are afflicted by this errata.

> I'm not thrilled with this, it's undocumented, the other workaround don't have
> it and I don't think that we really need it.

The B2BST errata workaround requires more changes to assembler routines 
commonly used by operating systems, such as for example register window 
handling, than what the UT699 workaround needed. It would be nice to 
have a way to only enable these modification when the -mfix- flag is 
used. The alternative would be to provide a define directly on the 
compiler command line in conjunction with -mfix flag. But if more 
changes are required later on it would be good to have the define more 
closely tied to the flag to minimize the number of changes to Makefiles 
and etc.

Would it be OK to add if we document it properly?

-- 
Daniel Cederman
Cobham Gaisler

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[David Miller]

From: Daniel Cederman <cederman@gaisler.com>
Date: Thu, 29 Jun 2017 17:15:43 +0200

>> I'm not thrilled with this, it's undocumented, the other workaround
>> don't have
>> it and I don't think that we really need it.
> 
> The B2BST errata workaround requires more changes to assembler
> routines commonly used by operating systems, such as for example
> register window handling, than what the UT699 workaround needed. It
> would be nice to have a way to only enable these modification when the
> -mfix- flag is used. The alternative would be to provide a define
> directly on the compiler command line in conjunction with -mfix
> flag. But if more changes are required later on it would be good to
> have the define more closely tied to the flag to minimize the number
> of changes to Makefiles and etc.

Personally, I have never seen compiler based CPP defines as ever being
useful for tailoring OS assembler code.  Ever.

In most cases you will want to support several families of CPUs and
therefore sort out the individual cpu support assembler routines
internally in the kernel sources.

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Sebastian Huber]

On 29/06/17 18:05, David Miller wrote:

> From: Daniel Cederman <cederman@gaisler.com>
> Date: Thu, 29 Jun 2017 17:15:43 +0200
>
>>> I'm not thrilled with this, it's undocumented, the other workaround
>>> don't have
>>> it and I don't think that we really need it.
>> The B2BST errata workaround requires more changes to assembler
>> routines commonly used by operating systems, such as for example
>> register window handling, than what the UT699 workaround needed. It
>> would be nice to have a way to only enable these modification when the
>> -mfix- flag is used. The alternative would be to provide a define
>> directly on the compiler command line in conjunction with -mfix
>> flag. But if more changes are required later on it would be good to
>> have the define more closely tied to the flag to minimize the number
>> of changes to Makefiles and etc.
> Personally, I have never seen compiler based CPP defines as ever being
> useful for tailoring OS assembler code.  Ever.
>
> In most cases you will want to support several families of CPUs and
> therefore sort out the individual cpu support assembler routines
> internally in the kernel sources.

This depends on the operating system you use. For some  embedded systems 
where the application and the operating system are one executable it is 
quite common to use compiler provided defines in assembly code.

For example:

https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=blob;f=newlib/libc/machine/arm/memcpy-armv7a.S;h=cd7962e075a30cb90ec073d77b177c3536429b9b;hb=HEAD

For a software development kit, the run-time libraries are built for a 
set of multilibs. Each assembler file may use multilib specific compiler 
defines, e.g. floating point unit present or not, errata XYZ present or 
not, etc.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Daniel Cederman]

On 2017-06-30 07:11, Sebastian Huber wrote:
> On 29/06/17 18:05, David Miller wrote:
> 
>> From: Daniel Cederman <cederman@gaisler.com>
>> Date: Thu, 29 Jun 2017 17:15:43 +0200
>>
>>>> I'm not thrilled with this, it's undocumented, the other workaround
>>>> don't have
>>>> it and I don't think that we really need it.
>>> The B2BST errata workaround requires more changes to assembler
>>> routines commonly used by operating systems, such as for example
>>> register window handling, than what the UT699 workaround needed. It
>>> would be nice to have a way to only enable these modification when the
>>> -mfix- flag is used. The alternative would be to provide a define
>>> directly on the compiler command line in conjunction with -mfix
>>> flag. But if more changes are required later on it would be good to
>>> have the define more closely tied to the flag to minimize the number
>>> of changes to Makefiles and etc.
>> Personally, I have never seen compiler based CPP defines as ever being
>> useful for tailoring OS assembler code.  Ever.
>>
>> In most cases you will want to support several families of CPUs and
>> therefore sort out the individual cpu support assembler routines
>> internally in the kernel sources.
> 
> This depends on the operating system you use. For some  embedded systems 
> where the application and the operating system are one executable it is 
> quite common to use compiler provided defines in assembly code.
> 
> For example:
> 
> https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=blob;f=newlib/libc/machine/arm/memcpy-armv7a.S;h=cd7962e075a30cb90ec073d77b177c3536429b9b;hb=HEAD 
> 
> 
> For a software development kit, the run-time libraries are built for a 
> set of multilibs. Each assembler file may use multilib specific compiler 
> defines, e.g. floating point unit present or not, errata XYZ present or 
> not, etc.
> 

We can drop the define if necessary, but we would like to keep the two 
flags. Would that be OK to apply?

-- 
Daniel Cederman
Cobham Gaisler

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Sebastian Huber]

On 04/07/17 15:38, Daniel Cederman wrote:
>
>
> On 2017-06-30 07:11, Sebastian Huber wrote:
>> On 29/06/17 18:05, David Miller wrote:
>>
>>> From: Daniel Cederman <cederman@gaisler.com>
>>> Date: Thu, 29 Jun 2017 17:15:43 +0200
>>>
>>>>> I'm not thrilled with this, it's undocumented, the other workaround
>>>>> don't have
>>>>> it and I don't think that we really need it.
>>>> The B2BST errata workaround requires more changes to assembler
>>>> routines commonly used by operating systems, such as for example
>>>> register window handling, than what the UT699 workaround needed. It
>>>> would be nice to have a way to only enable these modification when the
>>>> -mfix- flag is used. The alternative would be to provide a define
>>>> directly on the compiler command line in conjunction with -mfix
>>>> flag. But if more changes are required later on it would be good to
>>>> have the define more closely tied to the flag to minimize the number
>>>> of changes to Makefiles and etc.
>>> Personally, I have never seen compiler based CPP defines as ever being
>>> useful for tailoring OS assembler code.  Ever.
>>>
>>> In most cases you will want to support several families of CPUs and
>>> therefore sort out the individual cpu support assembler routines
>>> internally in the kernel sources.
>>
>> This depends on the operating system you use. For some  embedded 
>> systems where the application and the operating system are one 
>> executable it is quite common to use compiler provided defines in 
>> assembly code.
>>
>> For example:
>>
>> https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=blob;f=newlib/libc/machine/arm/memcpy-armv7a.S;h=cd7962e075a30cb90ec073d77b177c3536429b9b;hb=HEAD 
>>
>>
>> For a software development kit, the run-time libraries are built for 
>> a set of multilibs. Each assembler file may use multilib specific 
>> compiler defines, e.g. floating point unit present or not, errata XYZ 
>> present or not, etc.
>>
>
> We can drop the define if necessary, but we would like to keep the two 
> flags. Would that be OK to apply?
>

If I read the GRLIB-TN-0009 correctly, then we have to adjust the 
context switch, interrupt processing and window management code in 
RTEMS. So, we definitely need this define.

Since this errata affects actually the GRLIB, which is used in many 
products, should we really start adding -mfix-some-processor options? 
The GRLIB affected by this errata may be used in custom designs as well. 
I suggest to simply add a

-mfix-leon3ft-b2bst

option which enables the workaround and adds a builtin define

#define __FIX_LEON3FT_B2BST

The documentation for this option should mention this and also reference 
the GRLIB-TN-0009 and maybe the affected known processors.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Eric Botcazou]

> We can drop the define if necessary, but we would like to keep the two
> flags. Would that be OK to apply?

Yes, OK to apply on mainline and 7 branch with this change, thanks.

-- 
Eric Botcazou

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Daniel Cederman]

On 2017-07-07 12:01, Eric Botcazou wrote:
>> We can drop the define if necessary, but we would like to keep the two
>> flags. Would that be OK to apply?
> 
> Yes, OK to apply on mainline and 7 branch with this change, thanks.
> 

Great! Would you mind to apply the patch for us? The only person here 
with write access just went on vacation. I have submitted a new version 
(v4) with the change that applies to both main and 7.

-- 
Daniel Cederman
Cobham Gaisler

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Eric Botcazou]

> Great! Would you mind to apply the patch for us? The only person here
> with write access just went on vacation. I have submitted a new version
> (v4) with the change that applies to both main and 7.

OK, will do.

-- 
Eric Botcazou

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

[Daniel Cederman]

On 2017-07-07 18:04, Eric Botcazou wrote:
>> Great! Would you mind to apply the patch for us? The only person here
>> with write access just went on vacation. I have submitted a new version
>> (v4) with the change that applies to both main and 7.
> 
> OK, will do.
> 

Thanks!

-- 
Daniel Cederman
Cobham Gaisler