This patch eliminates the TARGET_UPPER_REGS_{DF,SF} macros. The next patch will eliminate TARGET_UPPER_REGS_DI. I had to tune the optimization that turned load into FPR register and then move to Altivec register (and the store equivalent) because it used TARGET_UPPER_REGS_ to protect SFmode on power7. I split the upper register patch for DImode because there were a few more cases (mostly involving VSX small integer support), and I will submit the patch after this one. As I'm posting this, the little endian power8 build has finished the bootstrap and is beginning the test phase, and big endian power7 is on stage 2. Assuming both systems show no regressions, is it ok to check this patch into the trunk? As I mentioned, my next patch will eliminate TARGET_UPPER_REGS_DI. I will probably tackle eliminating the VSX small integer option after that, and then eliminating the ISA 3.0 d-form options. 2017-07-24 Michael Meissner * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Eliminate TARGET_UPPER_REGS_{DF,DI} usage. * config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Poison macro. (TARGET_UPPER_REGS_SF): Likewise. * config/rs6000/rs6000.md (ALTIVEC_DFORM): Eliminate TARGET_UPPER_REGS_{DF,SF,DI} usage in optimizing DF/SF/DI memory references involving Altivec registers. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797