* [PATCH, cleanup] Remove PowerPC -mupper-regs-* options
@ 2017-07-22 6:46 Michael Meissner
2017-07-24 10:21 ` Segher Boessenkool
0 siblings, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-22 6:46 UTC (permalink / raw)
To: GCC Patches, Segher Boessenkool, David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 3969 bytes --]
The -mupper-regs-{df,di,sf} debug options that I added in previoius versions of
GCC to control whether DFmode, DImode, or SFmode could go in the traditional
Altivec registers has outlived its usefulness. This patch deletes the
options. I fixed up the various tests that used the option, and deleted
several tests that make no sense now that the options don't exist.
I have checked this with bootstrap builds and make check on a little endian
power8 system and a big endian power7 system. There were no regressions in any
of the tests.
One thing that I did was continue to define __UPPER_REGS_{DF,SF,DI}__ that were
previously defined. I can delete them if desired and perhaps poison the names
so that any use if flaged.
Future patches will include removal of the TARGET_UPPER_REGS_* macros in the
various files. I also plan to remove -mvsx-small-integer, and the various
-mpower9-dform* options.
Is this ok for trunk? At present, I do not intend to back port this to GCC 7
(but if the maintainers want that, I can do it).
[gcc]
2017-07-22 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete
upper-regs options.
(ISA_2_7_MASKS_SERVER): Likewise.
(ISA_3_0_MASKS_IEEE): Likewise.
(OTHER_P8_VECTOR_MASKS): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(power7 cpu): Use ISA_2_6_MASKS_SERVER instead of using a
duplicate list of options.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove
explicit -mupper-regs options. Define __UPPER_REGS_*__ based on
VSX or P8_VECTOR.
* config/rs6000/rs6000.opt (-mvsx-scalar-memory): Delete
-mupper-regs* options. Delete -mvsx-scalar-memory, which was an
alias for -mupper-regs-df.
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Define upper regs
options in terms of whether -mvsx or -mpower8-vector was used.
(TARGET_UPPER_REGS_DI): Likewise.
(TARGET_UPPER_REGS_SF): Likewise.
* doc/invoke.texi (RS/6000 and PowerPC Options): Delete the
-mupper-regs-* options.
[gcc/testsuite]
2017-07-22 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/pr65849-1.c: Delete, test no longer valid
since the upper-regs options have been deleted.
* gcc.target/powerpc/pr65849-2.c: Likewise.
* gcc.target/powerpc/pr80099-1.c: Likewise.
* gcc.target/powerpc/pr80099-2.c: Likewise.
* gcc.target/powerpc/pr80099-3.c: Likewise.
* gcc.target/powerpc/pr80099-4.c: Likewise.
* gcc.target/powerpc/pr80099-5.c: Likewise.
* gcc.target/powerpc/builtins-2-p9-runnable.c: Update test to
support removal of the upper-regs options.
* gcc.target/powerpc/p8vector-fp.c: Likewise.
* gcc.target/powerpc/p8vector-ldst.c: Likewise.
* gcc.target/powerpc/p9-dimode1.c: Likewise.
* gcc.target/powerpc/p9-dimode2.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-1.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-10.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-5.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-9.c: Likewise.
* gcc.target/powerpc/ppc-round.c: Likewise.
* gcc.target/powerpc/pr71720.c: Likewise.
* gcc.target/powerpc/pr72853.c: Likewise.
* gcc.target/powerpc/pr79907.c: Likewise.
* gcc.target/powerpc/pr78953.c: Likewise.
* gcc.target/powerpc/upper-regs-df.c: Likewise.
* gcc.target/powerpc/upper-regs-sf.c: Likewise.
* gcc.target/powerpc/vec-extract-1.c: Likewise.
* gcc.target/powerpc/vec-init-3.c: Likewise.
* gcc.target/powerpc/vec-init-6.c: Likewise.
* gcc.target/powerpc/vec-init-7.c: Likewise.
* gcc.target/powerpc/vec-set-char.c: Likewise.
* gcc.target/powerpc/vec-set-int.c: Likewise.
* gcc.target/powerpc/vec-set-short.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: cleanup.patch001b --]
[-- Type: text/plain, Size: 90221 bytes --]
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 250405)
+++ gcc/config/rs6000/rs6000-cpus.def (.../gcc/config/rs6000) (working copy)
@@ -44,9 +44,7 @@
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_ALTIVEC \
- | OPTION_MASK_VSX \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF)
+ | OPTION_MASK_VSX)
/* For now, don't provide an embedded version of ISA 2.07. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
@@ -58,7 +56,6 @@
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC \
- | OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX_SMALL_INTEGER)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
@@ -79,9 +76,6 @@
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF \
- | OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX_SMALL_INTEGER)
/* Flags that need to be turned off if -mno-power9-vector. */
@@ -94,8 +88,7 @@
#define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_CRYPTO \
- | OPTION_MASK_UPPER_REGS_SF) \
+ | OPTION_MASK_CRYPTO)
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
@@ -103,8 +96,6 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
| OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF \
| OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
@@ -160,9 +151,6 @@
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF \
- | OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX \
| OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
@@ -251,11 +239,7 @@ RS6000_CPU ("power6", PROCESSOR_POWER6,
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
-RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
- | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
- | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF
- | OPTION_MASK_UPPER_REGS_DI)
+RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 250405)
+++ gcc/config/rs6000/rs6000.opt (.../gcc/config/rs6000) (working copy)
@@ -200,9 +200,6 @@ mvsx-scalar-double
Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
-mvsx-scalar-memory
-Target Undocumented Report Alias(mupper-regs-df)
-
mvsx-align-128
Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64
@@ -549,22 +546,6 @@ mcompat-align-parm
Target Report Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment.
-mupper-regs-df
-Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
-Allow double variables in upper registers with -mcpu=power7 or -mvsx.
-
-mupper-regs-sf
-Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
-Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector.
-
-mupper-regs
-Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
-Allow float/double variables in upper registers if cpu allows it.
-
-mupper-regs-di
-Target Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags)
-Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx.
-
moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
Analyze and remove doubleword swaps from VSX computations.
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 250405)
+++ gcc/config/rs6000/rs6000-c.c (.../gcc/config/rs6000) (working copy)
@@ -575,39 +575,20 @@ rs6000_target_modify_macros (bool define
2. If TARGET_ALTIVEC is turned off. */
if ((flags & OPTION_MASK_CRYPTO) != 0)
rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
- /* Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
- turned on in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned on and
- TARGET_VSX is turned on and OPTION_MASK_UPPER_REGS_DF is not
- explicitly turned off. Hereafter, the
- OPTION_MASK_UPPER_REGS_DF flag is considered to have been
- explicitly set.
- Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
- turned off in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned off and TARGET_VSX
- is turned on and OPTION_MASK_UPPER_REGS_DF is not explicitly
- turned on. Hereafter, the OPTION_MASK_UPPER_REGS_DF flag is
- considered to have been explicitly cleared.
- 2. If TARGET_UPPER_REGS_DF is turned on but TARGET_VSX is turned
- off. */
- if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0)
- rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
- /* Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
- turned on in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned on and
- TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
- turned off explicitly. Hereafter, the
- OPTION_MASK_UPPER_REGS_SF flag is considered to have been
- explicitly set.
- Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
- turned off in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned off and
- TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
- turned off explicitly. Hereafter, the
- OPTION_MASK_UPPER_REGS_SF flag is considered to have been
- explicitly cleared.
- 2. If TARGET_P8_VECTOR is off. */
- if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0)
+ /* Note, previously __UPPER_REGS_DF__ was defined if the option
+ -mupper-regs-df was used and it was on by default for -mvsx. That option
+ is now eliminated, so set __UPPER_REGS_DF__ based on whether VSX was
+ set. */
+ if ((flags & OPTION_MASK_VSX) != 0)
+ {
+ rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
+ rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DI__");
+ }
+ /* Note, previously __UPPER_REGS_SF__ was defined if the option
+ -mupper-regs-df was used and it was on by default for -mvsx. That option
+ is now eliminated, so set __UPPER_REGS_DF__ based on whether VSX was
+ set. */
+ if ((flags & OPTION_MASK_P8_VECTOR) != 0)
rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
/* options from the builtin masks. */
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 250405)
+++ gcc/config/rs6000/rs6000.c (.../gcc/config/rs6000) (working copy)
@@ -2908,8 +2908,7 @@ rs6000_setup_reg_addr_masks (void)
&& !FLOAT128_VECTOR_P (m2)
&& !complex_p
&& !small_int_vsx_p
- && (m2 != DFmode || !TARGET_UPPER_REGS_DF)
- && (m2 != SFmode || !TARGET_UPPER_REGS_SF))
+ && (m2 != DFmode || !TARGET_UPPER_REGS_DF))
{
addr_mask |= RELOAD_REG_PRE_INCDEC;
@@ -3263,7 +3262,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
}
- if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */
+ if (TARGET_P8_VECTOR) /* SFmode */
{
rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
@@ -3458,13 +3457,13 @@ rs6000_init_hard_regno_mode_ok (bool glo
}
}
- if (TARGET_UPPER_REGS_DF)
- reg_addr[DFmode].scalar_in_vmx_p = true;
-
- if (TARGET_UPPER_REGS_DI)
- reg_addr[DImode].scalar_in_vmx_p = true;
+ if (TARGET_VSX)
+ {
+ reg_addr[DFmode].scalar_in_vmx_p = true;
+ reg_addr[DImode].scalar_in_vmx_p = true;
+ }
- if (TARGET_UPPER_REGS_SF)
+ if (TARGET_P8_VECTOR)
reg_addr[SFmode].scalar_in_vmx_p = true;
if (TARGET_VSX_SMALL_INTEGER)
@@ -4277,18 +4276,10 @@ rs6000_option_override_internal (bool gl
{
if (cpu_index == PROCESSOR_POWER9)
{
- /* legacy behavior: allow -mcpu-power9 with certain
+ /* legacy behavior: allow -mcpu=power9 with certain
capabilities explicitly disabled. */
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
- /* However, reject this automatic fix if certain
- capabilities required for TARGET_P9_MINMAX support
- have been explicitly disabled. */
- if (((OPTION_MASK_VSX | OPTION_MASK_UPPER_REGS_SF
- | OPTION_MASK_UPPER_REGS_DF) & rs6000_isa_flags)
- != (OPTION_MASK_VSX | OPTION_MASK_UPPER_REGS_SF
- | OPTION_MASK_UPPER_REGS_DF))
- error ("-mpower9-minmax incompatible with explicitly disabled options");
- }
+ }
else
error ("Power9 target option is incompatible with -mcpu=<xxx> for "
"<xxx> less than power9");
@@ -4374,73 +4365,6 @@ rs6000_option_override_internal (bool gl
rs6000_isa_flags &= ~OPTION_MASK_DFP;
}
- /* Allow an explicit -mupper-regs to set -mupper-regs-df, -mupper-regs-di,
- and -mupper-regs-sf, depending on the cpu, unless the user explicitly also
- set the individual option. */
- if (TARGET_UPPER_REGS > 0)
- {
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
- {
- rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_DF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
- }
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI))
- {
- rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_DI;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DI;
- }
- if (TARGET_P8_VECTOR
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
- {
- rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_SF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
- }
- }
- else if (TARGET_UPPER_REGS == 0)
- {
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
- {
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
- }
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI))
- {
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DI;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DI;
- }
- if (TARGET_P8_VECTOR
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
- {
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
- }
- }
-
- if (TARGET_UPPER_REGS_DF && !TARGET_VSX)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
- error ("-mupper-regs-df requires -mvsx");
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
- }
-
- if (TARGET_UPPER_REGS_DI && !TARGET_VSX)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI)
- error ("-mupper-regs-di requires -mvsx");
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DI;
- }
-
- if (TARGET_UPPER_REGS_SF && !TARGET_P8_VECTOR)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF)
- error ("-mupper-regs-sf requires -mpower8-vector");
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
- }
-
/* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
silently turn off quad memory mode. */
if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
@@ -4649,24 +4573,6 @@ rs6000_option_override_internal (bool gl
}
}
- if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
- {
- /* We prefer to not mention undocumented options in
- error messages. However, if users have managed to select
- power9-dform without selecting upper-regs-df, they
- already know about undocumented flags. */
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
- error ("-mpower9-dform requires -mupper-regs-df");
- rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
- }
-
- if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_SF)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF)
- error ("-mpower9-dform requires -mupper-regs-sf");
- rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
- }
-
/* Enable LRA by default. */
if ((rs6000_isa_flags_explicit & OPTION_MASK_LRA) == 0)
rs6000_isa_flags |= OPTION_MASK_LRA;
@@ -36358,9 +36264,6 @@ static struct rs6000_opt_mask const rs60
{ "string", OPTION_MASK_STRING, false, true },
{ "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
- { "upper-regs-di", OPTION_MASK_UPPER_REGS_DI, false, true },
- { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, true },
- { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, true },
{ "vsx", OPTION_MASK_VSX, false, true },
{ "vsx-small-integer", OPTION_MASK_VSX_SMALL_INTEGER, false, true },
{ "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 250405)
+++ gcc/config/rs6000/rs6000.h (.../gcc/config/rs6000) (working copy)
@@ -571,6 +571,14 @@ extern int rs6000_vector_align[];
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
+/* We previously had -mupper-regs-{df,di,sf} to control whether DFmode, DImode,
+ and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted
+ these options. In order to simplify the code, define the options in terms
+ of the base option (vsx, power8-vector). */
+#define TARGET_UPPER_REGS_DF TARGET_VSX
+#define TARGET_UPPER_REGS_DI TARGET_VSX
+#define TARGET_UPPER_REGS_SF TARGET_P8_VECTOR
+
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */
@@ -602,7 +610,6 @@ extern int rs6000_vector_align[];
#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
&& TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
-
/* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
#define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
#define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/doc) (revision 250405)
+++ gcc/doc/invoke.texi (.../gcc/doc) (working copy)
@@ -1045,9 +1045,6 @@ See RS/6000 and PowerPC Options.
-mquad-memory -mno-quad-memory @gol
-mquad-memory-atomic -mno-quad-memory-atomic @gol
-mcompat-align-parm -mno-compat-align-parm @gol
--mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
--mupper-regs-di -mno-upper-regs-di @gol
--mupper-regs -mno-upper-regs @gol
-mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol
-mgnu-attribute -mno-gnu-attribute @gol
-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol
@@ -21899,50 +21896,6 @@ Generate code that uses (does not use) t
instructions. The @option{-mquad-memory-atomic} option requires use of
64-bit mode.
-@item -mupper-regs-di
-@itemx -mno-upper-regs-di
-@opindex mupper-regs-di
-@opindex mno-upper-regs-di
-Generate code that uses (does not use) the scalar instructions that
-target all 64 registers in the vector/scalar floating point register
-set that were added in version 2.06 of the PowerPC ISA when processing
-integers. @option{-mupper-regs-di} is turned on by default if you use
-any of the @option{-mcpu=power7}, @option{-mcpu=power8},
-@option{-mcpu=power9}, or @option{-mvsx} options.
-
-@item -mupper-regs-df
-@itemx -mno-upper-regs-df
-@opindex mupper-regs-df
-@opindex mno-upper-regs-df
-Generate code that uses (does not use) the scalar double precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.06 of the
-PowerPC ISA. @option{-mupper-regs-df} is turned on by default if you
-use any of the @option{-mcpu=power7}, @option{-mcpu=power8},
-@option{-mcpu=power9}, or @option{-mvsx} options.
-
-@item -mupper-regs-sf
-@itemx -mno-upper-regs-sf
-@opindex mupper-regs-sf
-@opindex mno-upper-regs-sf
-Generate code that uses (does not use) the scalar single precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.07 of the
-PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you
-use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or
-@option{-mcpu=power9} options.
-
-@item -mupper-regs
-@itemx -mno-upper-regs
-@opindex mupper-regs
-@opindex mno-upper-regs
-Generate code that uses (does not use) the scalar
-instructions that target all 64 registers in the vector/scalar
-floating point register set, depending on the model of the machine.
-
-If the @option{-mno-upper-regs} option is used, it turns off both
-@option{-mupper-regs-sf} and @option{-mupper-regs-df} options.
-
@item -mfloat128
@itemx -mno-float128
@opindex mfloat128
Index: gcc/testsuite/gcc.target/powerpc/pr80099-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-1.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-1.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,12 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* PR target/80099: compiler internal error if -mno-upper-regs-sf used. */
-
-int a;
-int int_from_mem (vector float *c)
-{
- return __builtin_vec_extract (*c, a);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr80099-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-2.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-2.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/p8vector-fp.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */
+/* { dg-options "-mcpu=power8 -O2 -fno-math-errno" } */
float abs_sf (float *p)
{
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,12 +2,12 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "fctidz" 2 } } */
-/* { dg-final { scan-assembler-not "lwz" } } */
-/* { dg-final { scan-assembler-not "stw" } } */
-/* { dg-final { scan-assembler-not "ld " } } */
-/* { dg-final { scan-assembler-not "std" } } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
+/* { dg-final { scan-assembler-not {\mld\M} } } */
+/* { dg-final { scan-assembler-not {\mstd\M} } } */
void float_to_llong (long long *dest, float src) { *dest = (long long) src; }
void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
Index: gcc/testsuite/gcc.target/powerpc/pr80099-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-3.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-3.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-df" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,10 +2,10 @@
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
+/* { dg-options "-mcpu=power8 -O2" } */
-/* Test for the -mupper-regs-df option to make sure double values are allocated
- to the Altivec registers as well as the traditional FPR registers. */
+/* Test make sure single precision values are allocated to the Altivec
+ registers as well as the traditional FPR registers. */
#ifndef TYPE
#define TYPE float
Index: gcc/testsuite/gcc.target/powerpc/p9-dimode1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-dimode1.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p9-dimode1.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
/* Verify P9 changes to allow DImode into Altivec registers, and generate
constants using XXSPLTIB. */
@@ -43,8 +43,8 @@ p9_minus_1 (void)
return ret;
}
-/* { dg-final { scan-assembler "\[ \t\]xxspltib" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]mtvsrd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */
+/* { dg-final { scan-assembler {\mxxspltib\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mlfd\M} } } */
+/* { dg-final { scan-assembler-not {\mld\M} } } */
+/* { dg-final { scan-assembler-not {\mlxsd\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr80099-4.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-4.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-4.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-di" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/p9-dimode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-dimode2.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p9-dimode2.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
/* Verify that large integer constants are loaded via direct move instead of being
loaded from memory. */
@@ -21,7 +21,7 @@ p9_large (void)
return ret;
}
-/* { dg-final { scan-assembler "\[ \t\]mtvsrd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */
+/* { dg-final { scan-assembler {\mmtvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mld\M} } } */
+/* { dg-final { scan-assembler-not {\mlfd\M} } } */
+/* { dg-final { scan-assembler-not {\mlxsd\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr72853.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr72853.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr72853.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O3 -mupper-regs-df -mupper-regs-sf -funroll-loops" } */
+/* { dg-options "-mcpu=power9 -O3 -funroll-loops" } */
/* derived from 20021120-1.c, compiled for -mcpu=power9. */
Index: gcc/testsuite/gcc.target/powerpc/pr80099-5.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-5.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-5.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr79907.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr79907.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr79907.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O3 -mno-upper-regs-df" } */
+/* { dg-options "-mcpu=power8 -O3" } */
int foo (short a[], int x)
{
Index: gcc/testsuite/gcc.target/powerpc/pr65849-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-1.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-1.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,728 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-mcpu=power7 -O2 -mno-upper-regs-df" } */
-
-/* Test whether we can enable the -mupper-regs-df with target pragmas. Make
- sure double values are allocated to the Altivec registers as well as the
- traditional FPR registers. */
-
-#ifndef TYPE
-#define TYPE double
-#endif
-
-#ifndef MASK_TYPE
-#define MASK_TYPE unsigned long long
-#endif
-
-#define MASK_ONE ((MASK_TYPE)1)
-#define ZERO ((TYPE) 0.0)
-
-#pragma GCC target ("upper-regs-df")
-TYPE
-test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
- const MASK_TYPE *sub_mask, const TYPE *sub_values,
- const MASK_TYPE *mul_mask, const TYPE *mul_values,
- const MASK_TYPE *div_mask, const TYPE *div_values,
- const MASK_TYPE *eq0_mask, int *eq0_ptr)
-{
- TYPE value;
- TYPE value00 = ZERO;
- TYPE value01 = ZERO;
- TYPE value02 = ZERO;
- TYPE value03 = ZERO;
- TYPE value04 = ZERO;
- TYPE value05 = ZERO;
- TYPE value06 = ZERO;
- TYPE value07 = ZERO;
- TYPE value08 = ZERO;
- TYPE value09 = ZERO;
- TYPE value10 = ZERO;
- TYPE value11 = ZERO;
- TYPE value12 = ZERO;
- TYPE value13 = ZERO;
- TYPE value14 = ZERO;
- TYPE value15 = ZERO;
- TYPE value16 = ZERO;
- TYPE value17 = ZERO;
- TYPE value18 = ZERO;
- TYPE value19 = ZERO;
- TYPE value20 = ZERO;
- TYPE value21 = ZERO;
- TYPE value22 = ZERO;
- TYPE value23 = ZERO;
- TYPE value24 = ZERO;
- TYPE value25 = ZERO;
- TYPE value26 = ZERO;
- TYPE value27 = ZERO;
- TYPE value28 = ZERO;
- TYPE value29 = ZERO;
- TYPE value30 = ZERO;
- TYPE value31 = ZERO;
- TYPE value32 = ZERO;
- TYPE value33 = ZERO;
- TYPE value34 = ZERO;
- TYPE value35 = ZERO;
- TYPE value36 = ZERO;
- TYPE value37 = ZERO;
- TYPE value38 = ZERO;
- TYPE value39 = ZERO;
- MASK_TYPE mask;
- int eq0;
-
- while ((mask = *add_mask++) != 0)
- {
- value = *add_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 += value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 += value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 += value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 += value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 += value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 += value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 += value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 += value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 += value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 += value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 += value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 += value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 += value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 += value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 += value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 += value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 += value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 += value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 += value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 += value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 += value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 += value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 += value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 += value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 += value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 += value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 += value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 += value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 += value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 += value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 += value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 += value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 += value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 += value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 += value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 += value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 += value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 += value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 += value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 += value;
- }
-
- while ((mask = *sub_mask++) != 0)
- {
- value = *sub_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 -= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 -= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 -= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 -= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 -= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 -= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 -= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 -= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 -= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 -= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 -= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 -= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 -= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 -= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 -= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 -= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 -= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 -= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 -= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 -= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 -= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 -= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 -= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 -= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 -= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 -= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 -= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 -= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 -= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 -= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 -= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 -= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 -= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 -= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 -= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 -= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 -= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 -= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 -= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 -= value;
- }
-
- while ((mask = *mul_mask++) != 0)
- {
- value = *mul_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 *= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 *= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 *= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 *= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 *= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 *= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 *= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 *= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 *= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 *= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 *= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 *= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 *= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 *= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 *= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 *= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 *= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 *= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 *= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 *= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 *= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 *= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 *= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 *= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 *= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 *= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 *= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 *= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 *= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 *= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 *= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 *= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 *= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 *= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 *= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 *= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 *= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 *= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 *= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 *= value;
- }
-
- while ((mask = *div_mask++) != 0)
- {
- value = *div_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 /= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 /= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 /= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 /= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 /= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 /= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 /= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 /= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 /= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 /= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 /= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 /= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 /= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 /= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 /= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 /= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 /= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 /= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 /= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 /= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 /= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 /= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 /= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 /= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 /= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 /= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 /= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 /= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 /= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 /= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 /= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 /= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 /= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 /= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 /= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 /= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 /= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 /= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 /= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 /= value;
- }
-
- while ((mask = *eq0_mask++) != 0)
- {
- eq0 = 0;
-
- if ((mask & (MASK_ONE << 0)) != 0)
- eq0 |= (value00 == ZERO);
-
- if ((mask & (MASK_ONE << 1)) != 0)
- eq0 |= (value01 == ZERO);
-
- if ((mask & (MASK_ONE << 2)) != 0)
- eq0 |= (value02 == ZERO);
-
- if ((mask & (MASK_ONE << 3)) != 0)
- eq0 |= (value03 == ZERO);
-
- if ((mask & (MASK_ONE << 4)) != 0)
- eq0 |= (value04 == ZERO);
-
- if ((mask & (MASK_ONE << 5)) != 0)
- eq0 |= (value05 == ZERO);
-
- if ((mask & (MASK_ONE << 6)) != 0)
- eq0 |= (value06 == ZERO);
-
- if ((mask & (MASK_ONE << 7)) != 0)
- eq0 |= (value07 == ZERO);
-
- if ((mask & (MASK_ONE << 8)) != 0)
- eq0 |= (value08 == ZERO);
-
- if ((mask & (MASK_ONE << 9)) != 0)
- eq0 |= (value09 == ZERO);
-
- if ((mask & (MASK_ONE << 10)) != 0)
- eq0 |= (value10 == ZERO);
-
- if ((mask & (MASK_ONE << 11)) != 0)
- eq0 |= (value11 == ZERO);
-
- if ((mask & (MASK_ONE << 12)) != 0)
- eq0 |= (value12 == ZERO);
-
- if ((mask & (MASK_ONE << 13)) != 0)
- eq0 |= (value13 == ZERO);
-
- if ((mask & (MASK_ONE << 14)) != 0)
- eq0 |= (value14 == ZERO);
-
- if ((mask & (MASK_ONE << 15)) != 0)
- eq0 |= (value15 == ZERO);
-
- if ((mask & (MASK_ONE << 16)) != 0)
- eq0 |= (value16 == ZERO);
-
- if ((mask & (MASK_ONE << 17)) != 0)
- eq0 |= (value17 == ZERO);
-
- if ((mask & (MASK_ONE << 18)) != 0)
- eq0 |= (value18 == ZERO);
-
- if ((mask & (MASK_ONE << 19)) != 0)
- eq0 |= (value19 == ZERO);
-
- if ((mask & (MASK_ONE << 20)) != 0)
- eq0 |= (value20 == ZERO);
-
- if ((mask & (MASK_ONE << 21)) != 0)
- eq0 |= (value21 == ZERO);
-
- if ((mask & (MASK_ONE << 22)) != 0)
- eq0 |= (value22 == ZERO);
-
- if ((mask & (MASK_ONE << 23)) != 0)
- eq0 |= (value23 == ZERO);
-
- if ((mask & (MASK_ONE << 24)) != 0)
- eq0 |= (value24 == ZERO);
-
- if ((mask & (MASK_ONE << 25)) != 0)
- eq0 |= (value25 == ZERO);
-
- if ((mask & (MASK_ONE << 26)) != 0)
- eq0 |= (value26 == ZERO);
-
- if ((mask & (MASK_ONE << 27)) != 0)
- eq0 |= (value27 == ZERO);
-
- if ((mask & (MASK_ONE << 28)) != 0)
- eq0 |= (value28 == ZERO);
-
- if ((mask & (MASK_ONE << 29)) != 0)
- eq0 |= (value29 == ZERO);
-
- if ((mask & (MASK_ONE << 30)) != 0)
- eq0 |= (value30 == ZERO);
-
- if ((mask & (MASK_ONE << 31)) != 0)
- eq0 |= (value31 == ZERO);
-
- if ((mask & (MASK_ONE << 32)) != 0)
- eq0 |= (value32 == ZERO);
-
- if ((mask & (MASK_ONE << 33)) != 0)
- eq0 |= (value33 == ZERO);
-
- if ((mask & (MASK_ONE << 34)) != 0)
- eq0 |= (value34 == ZERO);
-
- if ((mask & (MASK_ONE << 35)) != 0)
- eq0 |= (value35 == ZERO);
-
- if ((mask & (MASK_ONE << 36)) != 0)
- eq0 |= (value36 == ZERO);
-
- if ((mask & (MASK_ONE << 37)) != 0)
- eq0 |= (value37 == ZERO);
-
- if ((mask & (MASK_ONE << 38)) != 0)
- eq0 |= (value38 == ZERO);
-
- if ((mask & (MASK_ONE << 39)) != 0)
- eq0 |= (value39 == ZERO);
-
- *eq0_ptr++ = eq0;
- }
-
- return ( value00 + value01 + value02 + value03 + value04
- + value05 + value06 + value07 + value08 + value09
- + value10 + value11 + value12 + value13 + value14
- + value15 + value16 + value17 + value18 + value19
- + value20 + value21 + value22 + value23 + value24
- + value25 + value26 + value27 + value28 + value29
- + value30 + value31 + value32 + value33 + value34
- + value35 + value36 + value37 + value38 + value39);
-}
-
-/* { dg-final { scan-assembler "fadd" } } */
-/* { dg-final { scan-assembler "fsub" } } */
-/* { dg-final { scan-assembler "fmul" } } */
-/* { dg-final { scan-assembler "fdiv" } } */
-/* { dg-final { scan-assembler "fcmpu" } } */
-/* { dg-final { scan-assembler "xsadddp" } } */
-/* { dg-final { scan-assembler "xssubdp" } } */
-/* { dg-final { scan-assembler "xsmuldp" } } */
-/* { dg-final { scan-assembler "xsdivdp" } } */
-/* { dg-final { scan-assembler "xscmpudp" } } */
Index: gcc/testsuite/gcc.target/powerpc/pr78953.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr78953.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr78953.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
#include <altivec.h>
@@ -16,4 +16,4 @@ foo (vector int *vp, int *ip)
ip[4] = vec_extract (v, 0);
}
-/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */
+/* { dg-final { scan-assembler {\mxxextractuw\M|\mvextuw[lr]x\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr65849-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-2.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-2.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,728 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* Test whether we can enable the -mupper-regs-sf with target pragmas. Make
- sure float values are allocated to the Altivec registers as well as the
- traditional FPR registers. */
-
-#ifndef TYPE
-#define TYPE float
-#endif
-
-#ifndef MASK_TYPE
-#define MASK_TYPE unsigned long long
-#endif
-
-#define MASK_ONE ((MASK_TYPE)1)
-#define ZERO ((TYPE) 0.0)
-
-#pragma GCC target ("upper-regs-sf")
-TYPE
-test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
- const MASK_TYPE *sub_mask, const TYPE *sub_values,
- const MASK_TYPE *mul_mask, const TYPE *mul_values,
- const MASK_TYPE *div_mask, const TYPE *div_values,
- const MASK_TYPE *eq0_mask, int *eq0_ptr)
-{
- TYPE value;
- TYPE value00 = ZERO;
- TYPE value01 = ZERO;
- TYPE value02 = ZERO;
- TYPE value03 = ZERO;
- TYPE value04 = ZERO;
- TYPE value05 = ZERO;
- TYPE value06 = ZERO;
- TYPE value07 = ZERO;
- TYPE value08 = ZERO;
- TYPE value09 = ZERO;
- TYPE value10 = ZERO;
- TYPE value11 = ZERO;
- TYPE value12 = ZERO;
- TYPE value13 = ZERO;
- TYPE value14 = ZERO;
- TYPE value15 = ZERO;
- TYPE value16 = ZERO;
- TYPE value17 = ZERO;
- TYPE value18 = ZERO;
- TYPE value19 = ZERO;
- TYPE value20 = ZERO;
- TYPE value21 = ZERO;
- TYPE value22 = ZERO;
- TYPE value23 = ZERO;
- TYPE value24 = ZERO;
- TYPE value25 = ZERO;
- TYPE value26 = ZERO;
- TYPE value27 = ZERO;
- TYPE value28 = ZERO;
- TYPE value29 = ZERO;
- TYPE value30 = ZERO;
- TYPE value31 = ZERO;
- TYPE value32 = ZERO;
- TYPE value33 = ZERO;
- TYPE value34 = ZERO;
- TYPE value35 = ZERO;
- TYPE value36 = ZERO;
- TYPE value37 = ZERO;
- TYPE value38 = ZERO;
- TYPE value39 = ZERO;
- MASK_TYPE mask;
- int eq0;
-
- while ((mask = *add_mask++) != 0)
- {
- value = *add_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 += value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 += value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 += value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 += value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 += value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 += value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 += value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 += value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 += value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 += value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 += value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 += value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 += value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 += value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 += value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 += value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 += value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 += value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 += value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 += value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 += value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 += value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 += value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 += value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 += value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 += value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 += value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 += value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 += value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 += value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 += value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 += value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 += value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 += value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 += value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 += value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 += value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 += value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 += value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 += value;
- }
-
- while ((mask = *sub_mask++) != 0)
- {
- value = *sub_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 -= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 -= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 -= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 -= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 -= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 -= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 -= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 -= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 -= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 -= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 -= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 -= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 -= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 -= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 -= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 -= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 -= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 -= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 -= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 -= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 -= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 -= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 -= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 -= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 -= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 -= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 -= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 -= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 -= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 -= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 -= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 -= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 -= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 -= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 -= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 -= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 -= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 -= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 -= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 -= value;
- }
-
- while ((mask = *mul_mask++) != 0)
- {
- value = *mul_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 *= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 *= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 *= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 *= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 *= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 *= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 *= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 *= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 *= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 *= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 *= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 *= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 *= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 *= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 *= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 *= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 *= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 *= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 *= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 *= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 *= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 *= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 *= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 *= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 *= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 *= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 *= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 *= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 *= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 *= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 *= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 *= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 *= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 *= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 *= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 *= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 *= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 *= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 *= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 *= value;
- }
-
- while ((mask = *div_mask++) != 0)
- {
- value = *div_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 /= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 /= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 /= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 /= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 /= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 /= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 /= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 /= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 /= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 /= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 /= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 /= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 /= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 /= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 /= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 /= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 /= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 /= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 /= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 /= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 /= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 /= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 /= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 /= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 /= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 /= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 /= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 /= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 /= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 /= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 /= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 /= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 /= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 /= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 /= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 /= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 /= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 /= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 /= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 /= value;
- }
-
- while ((mask = *eq0_mask++) != 0)
- {
- eq0 = 0;
-
- if ((mask & (MASK_ONE << 0)) != 0)
- eq0 |= (value00 == ZERO);
-
- if ((mask & (MASK_ONE << 1)) != 0)
- eq0 |= (value01 == ZERO);
-
- if ((mask & (MASK_ONE << 2)) != 0)
- eq0 |= (value02 == ZERO);
-
- if ((mask & (MASK_ONE << 3)) != 0)
- eq0 |= (value03 == ZERO);
-
- if ((mask & (MASK_ONE << 4)) != 0)
- eq0 |= (value04 == ZERO);
-
- if ((mask & (MASK_ONE << 5)) != 0)
- eq0 |= (value05 == ZERO);
-
- if ((mask & (MASK_ONE << 6)) != 0)
- eq0 |= (value06 == ZERO);
-
- if ((mask & (MASK_ONE << 7)) != 0)
- eq0 |= (value07 == ZERO);
-
- if ((mask & (MASK_ONE << 8)) != 0)
- eq0 |= (value08 == ZERO);
-
- if ((mask & (MASK_ONE << 9)) != 0)
- eq0 |= (value09 == ZERO);
-
- if ((mask & (MASK_ONE << 10)) != 0)
- eq0 |= (value10 == ZERO);
-
- if ((mask & (MASK_ONE << 11)) != 0)
- eq0 |= (value11 == ZERO);
-
- if ((mask & (MASK_ONE << 12)) != 0)
- eq0 |= (value12 == ZERO);
-
- if ((mask & (MASK_ONE << 13)) != 0)
- eq0 |= (value13 == ZERO);
-
- if ((mask & (MASK_ONE << 14)) != 0)
- eq0 |= (value14 == ZERO);
-
- if ((mask & (MASK_ONE << 15)) != 0)
- eq0 |= (value15 == ZERO);
-
- if ((mask & (MASK_ONE << 16)) != 0)
- eq0 |= (value16 == ZERO);
-
- if ((mask & (MASK_ONE << 17)) != 0)
- eq0 |= (value17 == ZERO);
-
- if ((mask & (MASK_ONE << 18)) != 0)
- eq0 |= (value18 == ZERO);
-
- if ((mask & (MASK_ONE << 19)) != 0)
- eq0 |= (value19 == ZERO);
-
- if ((mask & (MASK_ONE << 20)) != 0)
- eq0 |= (value20 == ZERO);
-
- if ((mask & (MASK_ONE << 21)) != 0)
- eq0 |= (value21 == ZERO);
-
- if ((mask & (MASK_ONE << 22)) != 0)
- eq0 |= (value22 == ZERO);
-
- if ((mask & (MASK_ONE << 23)) != 0)
- eq0 |= (value23 == ZERO);
-
- if ((mask & (MASK_ONE << 24)) != 0)
- eq0 |= (value24 == ZERO);
-
- if ((mask & (MASK_ONE << 25)) != 0)
- eq0 |= (value25 == ZERO);
-
- if ((mask & (MASK_ONE << 26)) != 0)
- eq0 |= (value26 == ZERO);
-
- if ((mask & (MASK_ONE << 27)) != 0)
- eq0 |= (value27 == ZERO);
-
- if ((mask & (MASK_ONE << 28)) != 0)
- eq0 |= (value28 == ZERO);
-
- if ((mask & (MASK_ONE << 29)) != 0)
- eq0 |= (value29 == ZERO);
-
- if ((mask & (MASK_ONE << 30)) != 0)
- eq0 |= (value30 == ZERO);
-
- if ((mask & (MASK_ONE << 31)) != 0)
- eq0 |= (value31 == ZERO);
-
- if ((mask & (MASK_ONE << 32)) != 0)
- eq0 |= (value32 == ZERO);
-
- if ((mask & (MASK_ONE << 33)) != 0)
- eq0 |= (value33 == ZERO);
-
- if ((mask & (MASK_ONE << 34)) != 0)
- eq0 |= (value34 == ZERO);
-
- if ((mask & (MASK_ONE << 35)) != 0)
- eq0 |= (value35 == ZERO);
-
- if ((mask & (MASK_ONE << 36)) != 0)
- eq0 |= (value36 == ZERO);
-
- if ((mask & (MASK_ONE << 37)) != 0)
- eq0 |= (value37 == ZERO);
-
- if ((mask & (MASK_ONE << 38)) != 0)
- eq0 |= (value38 == ZERO);
-
- if ((mask & (MASK_ONE << 39)) != 0)
- eq0 |= (value39 == ZERO);
-
- *eq0_ptr++ = eq0;
- }
-
- return ( value00 + value01 + value02 + value03 + value04
- + value05 + value06 + value07 + value08 + value09
- + value10 + value11 + value12 + value13 + value14
- + value15 + value16 + value17 + value18 + value19
- + value20 + value21 + value22 + value23 + value24
- + value25 + value26 + value27 + value28 + value29
- + value30 + value31 + value32 + value33 + value34
- + value35 + value36 + value37 + value38 + value39);
-}
-
-/* { dg-final { scan-assembler "fadds" } } */
-/* { dg-final { scan-assembler "fsubs" } } */
-/* { dg-final { scan-assembler "fmuls" } } */
-/* { dg-final { scan-assembler "fdivs" } } */
-/* { dg-final { scan-assembler "fcmpu" } } */
-/* { dg-final { scan-assembler "xsaddsp" } } */
-/* { dg-final { scan-assembler "xssubsp" } } */
-/* { dg-final { scan-assembler "xsmulsp" } } */
-/* { dg-final { scan-assembler "xsdivsp" } } */
-/* { dg-final { scan-assembler "xscmpudp" } } */
Index: gcc/testsuite/gcc.target/powerpc/ppc-round.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-round.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-round.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,15 +2,15 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "stfiwx" 4 } } */
-/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
-/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
-/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
-/* { dg-final { scan-assembler-times "fcfids " 2 } } */
-/* { dg-final { scan-assembler-not "lwz" } } */
-/* { dg-final { scan-assembler-not "stw" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
/* Make sure we don't have loads/stores to the GPR unit. */
double
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,8 +2,8 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler "friz" } } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler {\mfriz\M|\mxsrdpiz\M} } } */
double round_double_llong (double a)
{
Index: gcc/testsuite/gcc.target/powerpc/vec-set-int.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-int.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-int.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -3,7 +3,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector int
insert_0_0 (vector int v)
Index: gcc/testsuite/gcc.target/powerpc/pr71720.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr71720.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/pr71720.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat. */
Index: gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
#include <altivec.h> // vector
Index: gcc/testsuite/gcc.target/powerpc/vec-init-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-3.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-3.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector long
merge (long a, long b)
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,15 +2,13 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
-/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
-/* { dg-final { scan-assembler-times "fcfids " 3 } } */
-/* { dg-final { scan-assembler-times "fcfidus " 1 } } */
-/* { dg-final { scan-assembler-times "fcfid " 3 } } */
-/* { dg-final { scan-assembler-times "fcfidu " 1 } } */
-/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
-/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mfcfidus\M|\mxscvuxdsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mfcfidu\M|\mxscvuxddp\M} 1 } } */
void int_to_float (float *dest, int *src)
{
Index: gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
+/* { dg-options "-mcpu=power8 -O2" } */
float
load_store_sf (unsigned long num,
Index: gcc/testsuite/gcc.target/powerpc/vec-set-char.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-char.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-char.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -3,7 +3,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector char
insert_0_0 (vector char v)
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-1.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-1.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
#include <altivec.h>
Index: gcc/testsuite/gcc.target/powerpc/upper-regs-df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/upper-regs-df.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/upper-regs-df.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,10 +2,10 @@
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power7 -O2 -mupper-regs-df" } */
+/* { dg-options "-mcpu=power7 -O2" } */
-/* Test for the -mupper-regs-df option to make sure double values are allocated
- to the Altivec registers as well as the traditional FPR registers. */
+/* Test to make sure double values are allocated to the Altivec registers as
+ well as the traditional FPR registers. */
#ifndef TYPE
#define TYPE double
Index: gcc/testsuite/gcc.target/powerpc/vec-init-6.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-6.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-6.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
vector int
merge (int a, int b, int c, int d)
Index: gcc/testsuite/gcc.target/powerpc/vec-init-7.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-7.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-7.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
vector int
splat (int a)
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -2,13 +2,11 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
-/* { dg-final { scan-assembler-times "fctidz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiduz " 2 } } */
-/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
-/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiduz\M|\mxscvdpuxds\M} 2 } } */
void float_to_int (int *dest, float src) { *dest = (int) src; }
void double_to_int (int *dest, double src) { *dest = (int) src; }
Index: gcc/testsuite/gcc.target/powerpc/vec-set-short.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-short.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc) (revision 250405)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-short.c (.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -3,7 +3,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector short
insert_0_0 (vector short v)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH, cleanup] Remove PowerPC -mupper-regs-* options
2017-07-22 6:46 [PATCH, cleanup] Remove PowerPC -mupper-regs-* options Michael Meissner
@ 2017-07-24 10:21 ` Segher Boessenkool
2017-07-24 20:07 ` Michael Meissner
0 siblings, 1 reply; 19+ messages in thread
From: Segher Boessenkool @ 2017-07-24 10:21 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
Hi Mike,
On Sat, Jul 22, 2017 at 02:46:04AM -0400, Michael Meissner wrote:
> One thing that I did was continue to define __UPPER_REGS_{DF,SF,DI}__ that were
> previously defined. I can delete them if desired and perhaps poison the names
> so that any use if flaged.
I don't think anything uses it. Certainly nothing *should* use it: it
isn't documented anywhere :-) (Google doesn't find anything either, fwiw).
You can delete them I think. Poisoning is overkill.
> Future patches will include removal of the TARGET_UPPER_REGS_* macros in the
> various files. I also plan to remove -mvsx-small-integer, and the various
> -mpower9-dform* options.
Yay! Thank you.
> Is this ok for trunk? At present, I do not intend to back port this to GCC 7
> (but if the maintainers want that, I can do it).
I don't think that would help much, so yeah, let's not.
> @@ -58,7 +56,6 @@
> | OPTION_MASK_HTM \
> | OPTION_MASK_QUAD_MEMORY \
> | OPTION_MASK_QUAD_MEMORY_ATOMIC \
> - | OPTION_MASK_UPPER_REGS_SF \
> | OPTION_MASK_VSX_SMALL_INTEGER)
>
> /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
The OPTION_MASK_QUAD_MEMORY_ATOMIC line has errant leading spaces, maybe
you could fix that while at it.
> + /* Note, previously __UPPER_REGS_DF__ was defined if the option
> + -mupper-regs-df was used and it was on by default for -mvsx. That option
> + is now eliminated, so set __UPPER_REGS_DF__ based on whether VSX was
> + set. */
"That option" reads as refering to -mvsx.
> --- gcc/config/rs6000/rs6000.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 250405)
> +++ gcc/config/rs6000/rs6000.c (.../gcc/config/rs6000) (working copy)
> @@ -2908,8 +2908,7 @@ rs6000_setup_reg_addr_masks (void)
> && !FLOAT128_VECTOR_P (m2)
> && !complex_p
> && !small_int_vsx_p
> - && (m2 != DFmode || !TARGET_UPPER_REGS_DF)
> - && (m2 != SFmode || !TARGET_UPPER_REGS_SF))
> + && (m2 != DFmode || !TARGET_UPPER_REGS_DF))
> {
> addr_mask |= RELOAD_REG_PRE_INCDEC;
>
Why are you leaving DF here? (A later patch will take care of it, but
is it more than an oversight?)
> +/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
You could write {\m(fctidz|xscvdpsxds)\M} which may be easier to read.
Come to think of it, we could do e.g. {\m(lwz)\M} as well. Not sure
which is nicer.
Looks good, please commit! Thanks again,
Segher
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH, cleanup] Remove PowerPC -mupper-regs-* options
2017-07-24 10:21 ` Segher Boessenkool
@ 2017-07-24 20:07 ` Michael Meissner
2017-07-24 20:51 ` Segher Boessenkool
0 siblings, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-24 20:07 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 5889 bytes --]
On Mon, Jul 24, 2017 at 05:21:15AM -0500, Segher Boessenkool wrote:
> Hi Mike,
>
> On Sat, Jul 22, 2017 at 02:46:04AM -0400, Michael Meissner wrote:
> > One thing that I did was continue to define __UPPER_REGS_{DF,SF,DI}__ that were
> > previously defined. I can delete them if desired and perhaps poison the names
> > so that any use if flaged.
>
> I don't think anything uses it. Certainly nothing *should* use it: it
> isn't documented anywhere :-) (Google doesn't find anything either, fwiw).
>
> You can delete them I think. Poisoning is overkill.
Ok, deleted.
> > Future patches will include removal of the TARGET_UPPER_REGS_* macros in the
> > various files. I also plan to remove -mvsx-small-integer, and the various
> > -mpower9-dform* options.
>
> Yay! Thank you.
>
> > Is this ok for trunk? At present, I do not intend to back port this to GCC 7
> > (but if the maintainers want that, I can do it).
>
> I don't think that would help much, so yeah, let's not.
>
> > @@ -58,7 +56,6 @@
> > | OPTION_MASK_HTM \
> > | OPTION_MASK_QUAD_MEMORY \
> > | OPTION_MASK_QUAD_MEMORY_ATOMIC \
> > - | OPTION_MASK_UPPER_REGS_SF \
> > | OPTION_MASK_VSX_SMALL_INTEGER)
> >
> > /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
>
> The OPTION_MASK_QUAD_MEMORY_ATOMIC line has errant leading spaces, maybe
> you could fix that while at it.
Fixed.
> > + /* Note, previously __UPPER_REGS_DF__ was defined if the option
> > + -mupper-regs-df was used and it was on by default for -mvsx. That option
> > + is now eliminated, so set __UPPER_REGS_DF__ based on whether VSX was
> > + set. */
>
> "That option" reads as refering to -mvsx.
>
> > --- gcc/config/rs6000/rs6000.c (.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000) (revision 250405)
> > +++ gcc/config/rs6000/rs6000.c (.../gcc/config/rs6000) (working copy)
> > @@ -2908,8 +2908,7 @@ rs6000_setup_reg_addr_masks (void)
> > && !FLOAT128_VECTOR_P (m2)
> > && !complex_p
> > && !small_int_vsx_p
> > - && (m2 != DFmode || !TARGET_UPPER_REGS_DF)
> > - && (m2 != SFmode || !TARGET_UPPER_REGS_SF))
> > + && (m2 != DFmode || !TARGET_UPPER_REGS_DF))
> > {
> > addr_mask |= RELOAD_REG_PRE_INCDEC;
> >
> Why are you leaving DF here? (A later patch will take care of it, but
> is it more than an oversight?)
While this likely would be removed in the next patch, I deleted it now for
consistancy.
> > +/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
>
> You could write {\m(fctidz|xscvdpsxds)\M} which may be easier to read.
> Come to think of it, we could do e.g. {\m(lwz)\M} as well. Not sure
> which is nicer.
>
> Looks good, please commit! Thanks again,
I wasn't sure which form of regex (shell, grep, egrep) was used, and what
levels of quoting was needed, so I wrote it the other way.
Here is the patch I committed:
[gcc]
2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Delete
upper-regs options.
(ISA_2_7_MASKS_SERVER): Likewise.
(ISA_3_0_MASKS_IEEE): Likewise.
(OTHER_P8_VECTOR_MASKS): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
(power7 cpu): Use ISA_2_6_MASKS_SERVER instead of using a
duplicate list of options.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove
explicit -mupper-regs options.
* config/rs6000/rs6000.opt (-mvsx-scalar-memory): Delete
-mupper-regs* options. Delete -mvsx-scalar-memory, which was an
alias for -mupper-regs-df.
* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Define upper regs
options in terms of whether -mvsx or -mpower8-vector was used.
(TARGET_UPPER_REGS_DI): Likewise.
(TARGET_UPPER_REGS_SF): Likewise.
* doc/invoke.texi (RS/6000 and PowerPC Options): Delete the
-mupper-regs-* options.
[gcc/testsuite]
2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/pr65849-1.c: Delete, test no longer valid
since the upper-regs options have been deleted.
* gcc.target/powerpc/pr65849-2.c: Likewise.
* gcc.target/powerpc/pr80099-1.c: Likewise.
* gcc.target/powerpc/pr80099-2.c: Likewise.
* gcc.target/powerpc/pr80099-3.c: Likewise.
* gcc.target/powerpc/pr80099-4.c: Likewise.
* gcc.target/powerpc/pr80099-5.c: Likewise.
* gcc.target/powerpc/builtins-2-p9-runnable.c: Update test to
support removal of the upper-regs options.
* gcc.target/powerpc/p8vector-fp.c: Likewise.
* gcc.target/powerpc/p8vector-ldst.c: Likewise.
* gcc.target/powerpc/p9-dimode1.c: Likewise.
* gcc.target/powerpc/p9-dimode2.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-1.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-10.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-5.c: Likewise.
* gcc.target/powerpc/ppc-fpconv-9.c: Likewise.
* gcc.target/powerpc/ppc-round.c: Likewise.
* gcc.target/powerpc/pr71720.c: Likewise.
* gcc.target/powerpc/pr72853.c: Likewise.
* gcc.target/powerpc/pr79907.c: Likewise.
* gcc.target/powerpc/pr78953.c: Likewise.
* gcc.target/powerpc/upper-regs-df.c: Likewise.
* gcc.target/powerpc/upper-regs-sf.c: Likewise.
* gcc.target/powerpc/vec-extract-1.c: Likewise.
* gcc.target/powerpc/vec-init-3.c: Likewise.
* gcc.target/powerpc/vec-init-6.c: Likewise.
* gcc.target/powerpc/vec-init-7.c: Likewise.
* gcc.target/powerpc/vec-set-char.c: Likewise.
* gcc.target/powerpc/vec-set-int.c: Likewise.
* gcc.target/powerpc/vec-set-short.c: Likewise.
Now to remove the remaining TARGET_UPPER_REGS_* references.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: cleanup.patch002b --]
[-- Type: text/plain, Size: 85420 bytes --]
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c (revision 250478)
+++ gcc/config/rs6000/rs6000-c.c (working copy)
@@ -575,40 +575,6 @@ rs6000_target_modify_macros (bool define
2. If TARGET_ALTIVEC is turned off. */
if ((flags & OPTION_MASK_CRYPTO) != 0)
rs6000_define_or_undefine_macro (define_p, "__CRYPTO__");
- /* Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
- turned on in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned on and
- TARGET_VSX is turned on and OPTION_MASK_UPPER_REGS_DF is not
- explicitly turned off. Hereafter, the
- OPTION_MASK_UPPER_REGS_DF flag is considered to have been
- explicitly set.
- Note that the OPTION_MASK_UPPER_REGS_DF flag is automatically
- turned off in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned off and TARGET_VSX
- is turned on and OPTION_MASK_UPPER_REGS_DF is not explicitly
- turned on. Hereafter, the OPTION_MASK_UPPER_REGS_DF flag is
- considered to have been explicitly cleared.
- 2. If TARGET_UPPER_REGS_DF is turned on but TARGET_VSX is turned
- off. */
- if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0)
- rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__");
- /* Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
- turned on in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned on and
- TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
- turned off explicitly. Hereafter, the
- OPTION_MASK_UPPER_REGS_SF flag is considered to have been
- explicitly set.
- Note that the OPTION_MASK_UPPER_REGS_SF flag is automatically
- turned off in the following conditions:
- 1. If TARGET_UPPER_REGS is explicitly turned off and
- TARGET_P8_VECTOR is on and OPTION_MASK_UPPER_REGS_SF is not
- turned off explicitly. Hereafter, the
- OPTION_MASK_UPPER_REGS_SF flag is considered to have been
- explicitly cleared.
- 2. If TARGET_P8_VECTOR is off. */
- if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0)
- rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__");
/* options from the builtin masks. */
/* Note that RS6000_BTM_PAIRED is enabled only if
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def (revision 250478)
+++ gcc/config/rs6000/rs6000-cpus.def (working copy)
@@ -44,9 +44,7 @@
#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_ALTIVEC \
- | OPTION_MASK_VSX \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF)
+ | OPTION_MASK_VSX)
/* For now, don't provide an embedded version of ISA 2.07. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
@@ -57,8 +55,7 @@
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
- | OPTION_MASK_QUAD_MEMORY_ATOMIC \
- | OPTION_MASK_UPPER_REGS_SF \
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC \
| OPTION_MASK_VSX_SMALL_INTEGER)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
@@ -79,9 +76,6 @@
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF \
- | OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX_SMALL_INTEGER)
/* Flags that need to be turned off if -mno-power9-vector. */
@@ -94,8 +88,7 @@
#define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_CRYPTO \
- | OPTION_MASK_UPPER_REGS_SF) \
+ | OPTION_MASK_CRYPTO)
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
@@ -103,8 +96,6 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
| OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF \
| OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
@@ -160,9 +151,6 @@
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
- | OPTION_MASK_UPPER_REGS_DI \
- | OPTION_MASK_UPPER_REGS_DF \
- | OPTION_MASK_UPPER_REGS_SF \
| OPTION_MASK_VSX \
| OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
@@ -251,11 +239,7 @@ RS6000_CPU ("power6", PROCESSOR_POWER6,
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
-RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
- POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
- | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
- | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF
- | OPTION_MASK_UPPER_REGS_DI)
+RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 250478)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -2907,9 +2907,7 @@ rs6000_setup_reg_addr_masks (void)
&& !VECTOR_MODE_P (m2)
&& !FLOAT128_VECTOR_P (m2)
&& !complex_p
- && !small_int_vsx_p
- && (m2 != DFmode || !TARGET_UPPER_REGS_DF)
- && (m2 != SFmode || !TARGET_UPPER_REGS_SF))
+ && !small_int_vsx_p)
{
addr_mask |= RELOAD_REG_PRE_INCDEC;
@@ -3263,7 +3261,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
}
- if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */
+ if (TARGET_P8_VECTOR) /* SFmode */
{
rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
@@ -3458,13 +3456,13 @@ rs6000_init_hard_regno_mode_ok (bool glo
}
}
- if (TARGET_UPPER_REGS_DF)
- reg_addr[DFmode].scalar_in_vmx_p = true;
-
- if (TARGET_UPPER_REGS_DI)
- reg_addr[DImode].scalar_in_vmx_p = true;
+ if (TARGET_VSX)
+ {
+ reg_addr[DFmode].scalar_in_vmx_p = true;
+ reg_addr[DImode].scalar_in_vmx_p = true;
+ }
- if (TARGET_UPPER_REGS_SF)
+ if (TARGET_P8_VECTOR)
reg_addr[SFmode].scalar_in_vmx_p = true;
if (TARGET_VSX_SMALL_INTEGER)
@@ -4277,18 +4275,10 @@ rs6000_option_override_internal (bool gl
{
if (cpu_index == PROCESSOR_POWER9)
{
- /* legacy behavior: allow -mcpu-power9 with certain
+ /* legacy behavior: allow -mcpu=power9 with certain
capabilities explicitly disabled. */
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
- /* However, reject this automatic fix if certain
- capabilities required for TARGET_P9_MINMAX support
- have been explicitly disabled. */
- if (((OPTION_MASK_VSX | OPTION_MASK_UPPER_REGS_SF
- | OPTION_MASK_UPPER_REGS_DF) & rs6000_isa_flags)
- != (OPTION_MASK_VSX | OPTION_MASK_UPPER_REGS_SF
- | OPTION_MASK_UPPER_REGS_DF))
- error ("-mpower9-minmax incompatible with explicitly disabled options");
- }
+ }
else
error ("Power9 target option is incompatible with -mcpu=<xxx> for "
"<xxx> less than power9");
@@ -4374,73 +4364,6 @@ rs6000_option_override_internal (bool gl
rs6000_isa_flags &= ~OPTION_MASK_DFP;
}
- /* Allow an explicit -mupper-regs to set -mupper-regs-df, -mupper-regs-di,
- and -mupper-regs-sf, depending on the cpu, unless the user explicitly also
- set the individual option. */
- if (TARGET_UPPER_REGS > 0)
- {
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
- {
- rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_DF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
- }
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI))
- {
- rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_DI;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DI;
- }
- if (TARGET_P8_VECTOR
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
- {
- rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_SF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
- }
- }
- else if (TARGET_UPPER_REGS == 0)
- {
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
- {
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
- }
- if (TARGET_VSX
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI))
- {
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DI;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DI;
- }
- if (TARGET_P8_VECTOR
- && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
- {
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
- rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
- }
- }
-
- if (TARGET_UPPER_REGS_DF && !TARGET_VSX)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
- error ("-mupper-regs-df requires -mvsx");
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
- }
-
- if (TARGET_UPPER_REGS_DI && !TARGET_VSX)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DI)
- error ("-mupper-regs-di requires -mvsx");
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DI;
- }
-
- if (TARGET_UPPER_REGS_SF && !TARGET_P8_VECTOR)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF)
- error ("-mupper-regs-sf requires -mpower8-vector");
- rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
- }
-
/* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
silently turn off quad memory mode. */
if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
@@ -4649,24 +4572,6 @@ rs6000_option_override_internal (bool gl
}
}
- if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
- {
- /* We prefer to not mention undocumented options in
- error messages. However, if users have managed to select
- power9-dform without selecting upper-regs-df, they
- already know about undocumented flags. */
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
- error ("-mpower9-dform requires -mupper-regs-df");
- rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
- }
-
- if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_SF)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF)
- error ("-mpower9-dform requires -mupper-regs-sf");
- rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
- }
-
/* Enable LRA by default. */
if ((rs6000_isa_flags_explicit & OPTION_MASK_LRA) == 0)
rs6000_isa_flags |= OPTION_MASK_LRA;
@@ -36360,9 +36265,6 @@ static struct rs6000_opt_mask const rs60
{ "string", OPTION_MASK_STRING, false, true },
{ "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
- { "upper-regs-di", OPTION_MASK_UPPER_REGS_DI, false, true },
- { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, true },
- { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, true },
{ "vsx", OPTION_MASK_VSX, false, true },
{ "vsx-small-integer", OPTION_MASK_VSX_SMALL_INTEGER, false, true },
{ "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 250478)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -571,6 +571,14 @@ extern int rs6000_vector_align[];
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
+/* We previously had -mupper-regs-{df,di,sf} to control whether DFmode, DImode,
+ and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted
+ these options. In order to simplify the code, define the options in terms
+ of the base option (vsx, power8-vector). */
+#define TARGET_UPPER_REGS_DF TARGET_VSX
+#define TARGET_UPPER_REGS_DI TARGET_VSX
+#define TARGET_UPPER_REGS_SF TARGET_P8_VECTOR
+
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */
@@ -602,7 +610,6 @@ extern int rs6000_vector_align[];
#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
&& TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
-
/* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
#define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
#define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (revision 250478)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -200,9 +200,6 @@ mvsx-scalar-double
Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)
-mvsx-scalar-memory
-Target Undocumented Report Alias(mupper-regs-df)
-
mvsx-align-128
Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64
@@ -549,22 +546,6 @@ mcompat-align-parm
Target Report Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment.
-mupper-regs-df
-Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
-Allow double variables in upper registers with -mcpu=power7 or -mvsx.
-
-mupper-regs-sf
-Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
-Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector.
-
-mupper-regs
-Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
-Allow float/double variables in upper registers if cpu allows it.
-
-mupper-regs-di
-Target Report Mask(UPPER_REGS_DI) Var(rs6000_isa_flags)
-Allow 64-bit integer variables in upper registers with -mcpu=power7 or -mvsx.
-
moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
Analyze and remove doubleword swaps from VSX computations.
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 250478)
+++ gcc/doc/invoke.texi (working copy)
@@ -1045,9 +1045,6 @@ See RS/6000 and PowerPC Options.
-mquad-memory -mno-quad-memory @gol
-mquad-memory-atomic -mno-quad-memory-atomic @gol
-mcompat-align-parm -mno-compat-align-parm @gol
--mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
--mupper-regs-di -mno-upper-regs-di @gol
--mupper-regs -mno-upper-regs @gol
-mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol
-mgnu-attribute -mno-gnu-attribute @gol
-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol
@@ -21904,50 +21901,6 @@ Generate code that uses (does not use) t
instructions. The @option{-mquad-memory-atomic} option requires use of
64-bit mode.
-@item -mupper-regs-di
-@itemx -mno-upper-regs-di
-@opindex mupper-regs-di
-@opindex mno-upper-regs-di
-Generate code that uses (does not use) the scalar instructions that
-target all 64 registers in the vector/scalar floating point register
-set that were added in version 2.06 of the PowerPC ISA when processing
-integers. @option{-mupper-regs-di} is turned on by default if you use
-any of the @option{-mcpu=power7}, @option{-mcpu=power8},
-@option{-mcpu=power9}, or @option{-mvsx} options.
-
-@item -mupper-regs-df
-@itemx -mno-upper-regs-df
-@opindex mupper-regs-df
-@opindex mno-upper-regs-df
-Generate code that uses (does not use) the scalar double precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.06 of the
-PowerPC ISA. @option{-mupper-regs-df} is turned on by default if you
-use any of the @option{-mcpu=power7}, @option{-mcpu=power8},
-@option{-mcpu=power9}, or @option{-mvsx} options.
-
-@item -mupper-regs-sf
-@itemx -mno-upper-regs-sf
-@opindex mupper-regs-sf
-@opindex mno-upper-regs-sf
-Generate code that uses (does not use) the scalar single precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.07 of the
-PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you
-use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or
-@option{-mcpu=power9} options.
-
-@item -mupper-regs
-@itemx -mno-upper-regs
-@opindex mupper-regs
-@opindex mno-upper-regs
-Generate code that uses (does not use) the scalar
-instructions that target all 64 registers in the vector/scalar
-floating point register set, depending on the model of the machine.
-
-If the @option{-mno-upper-regs} option is used, it turns off both
-@option{-mupper-regs-sf} and @option{-mupper-regs-df} options.
-
@item -mfloat128
@itemx -mno-float128
@opindex mfloat128
Index: gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/builtins-2-p9-runnable.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc64*-*-* && { lp64 && p9vector_hw } } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
#include <altivec.h> // vector
Index: gcc/testsuite/gcc.target/powerpc/p8vector-fp.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/p8vector-fp.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */
+/* { dg-options "-mcpu=power8 -O2 -fno-math-errno" } */
float abs_sf (float *p)
{
Index: gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
+/* { dg-options "-mcpu=power8 -O2" } */
float
load_store_sf (unsigned long num,
Index: gcc/testsuite/gcc.target/powerpc/p9-dimode1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-dimode1.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/p9-dimode1.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
/* Verify P9 changes to allow DImode into Altivec registers, and generate
constants using XXSPLTIB. */
@@ -43,8 +43,8 @@ p9_minus_1 (void)
return ret;
}
-/* { dg-final { scan-assembler "\[ \t\]xxspltib" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]mtvsrd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */
+/* { dg-final { scan-assembler {\mxxspltib\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mlfd\M} } } */
+/* { dg-final { scan-assembler-not {\mld\M} } } */
+/* { dg-final { scan-assembler-not {\mlxsd\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/p9-dimode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-dimode2.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/p9-dimode2.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
/* Verify that large integer constants are loaded via direct move instead of being
loaded from memory. */
@@ -21,7 +21,7 @@ p9_large (void)
return ret;
}
-/* { dg-final { scan-assembler "\[ \t\]mtvsrd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]ld" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lfd" } } */
-/* { dg-final { scan-assembler-not "\[ \t\]lxsd" } } */
+/* { dg-final { scan-assembler {\mmtvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mld\M} } } */
+/* { dg-final { scan-assembler-not {\mlfd\M} } } */
+/* { dg-final { scan-assembler-not {\mlxsd\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c (working copy)
@@ -2,15 +2,13 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
-/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
-/* { dg-final { scan-assembler-times "fcfids " 3 } } */
-/* { dg-final { scan-assembler-times "fcfidus " 1 } } */
-/* { dg-final { scan-assembler-times "fcfid " 3 } } */
-/* { dg-final { scan-assembler-times "fcfidu " 1 } } */
-/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
-/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mfcfidus\M|\mxscvuxdsp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mfcfidu\M|\mxscvuxddp\M} 1 } } */
void int_to_float (float *dest, int *src)
{
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c (working copy)
@@ -2,8 +2,8 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler "friz" } } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler {\mfriz\M|\mxsrdpiz\M} } } */
double round_double_llong (double a)
{
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c (working copy)
@@ -2,13 +2,11 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
-/* { dg-final { scan-assembler-times "fctidz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiduz " 2 } } */
-/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
-/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiduz\M|\mxscvdpuxds\M} 2 } } */
void float_to_int (int *dest, float src) { *dest = (int) src; }
void double_to_int (int *dest, double src) { *dest = (int) src; }
Index: gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c (working copy)
@@ -2,12 +2,12 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "fctidz" 2 } } */
-/* { dg-final { scan-assembler-not "lwz" } } */
-/* { dg-final { scan-assembler-not "stw" } } */
-/* { dg-final { scan-assembler-not "ld " } } */
-/* { dg-final { scan-assembler-not "std" } } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
+/* { dg-final { scan-assembler-not {\mld\M} } } */
+/* { dg-final { scan-assembler-not {\mstd\M} } } */
void float_to_llong (long long *dest, float src) { *dest = (long long) src; }
void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
Index: gcc/testsuite/gcc.target/powerpc/ppc-round.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-round.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/ppc-round.c (working copy)
@@ -2,15 +2,15 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-O2 -mcpu=power7 -mno-upper-regs-df" } */
-/* { dg-final { scan-assembler-times "stfiwx" 4 } } */
-/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
-/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
-/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
-/* { dg-final { scan-assembler-times "fcfids " 2 } } */
-/* { dg-final { scan-assembler-not "lwz" } } */
-/* { dg-final { scan-assembler-not "stw" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
/* Make sure we don't have loads/stores to the GPR unit. */
double
Index: gcc/testsuite/gcc.target/powerpc/pr65849-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-1.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-1.c (working copy)
@@ -1,728 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
-/* { dg-options "-mcpu=power7 -O2 -mno-upper-regs-df" } */
-
-/* Test whether we can enable the -mupper-regs-df with target pragmas. Make
- sure double values are allocated to the Altivec registers as well as the
- traditional FPR registers. */
-
-#ifndef TYPE
-#define TYPE double
-#endif
-
-#ifndef MASK_TYPE
-#define MASK_TYPE unsigned long long
-#endif
-
-#define MASK_ONE ((MASK_TYPE)1)
-#define ZERO ((TYPE) 0.0)
-
-#pragma GCC target ("upper-regs-df")
-TYPE
-test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
- const MASK_TYPE *sub_mask, const TYPE *sub_values,
- const MASK_TYPE *mul_mask, const TYPE *mul_values,
- const MASK_TYPE *div_mask, const TYPE *div_values,
- const MASK_TYPE *eq0_mask, int *eq0_ptr)
-{
- TYPE value;
- TYPE value00 = ZERO;
- TYPE value01 = ZERO;
- TYPE value02 = ZERO;
- TYPE value03 = ZERO;
- TYPE value04 = ZERO;
- TYPE value05 = ZERO;
- TYPE value06 = ZERO;
- TYPE value07 = ZERO;
- TYPE value08 = ZERO;
- TYPE value09 = ZERO;
- TYPE value10 = ZERO;
- TYPE value11 = ZERO;
- TYPE value12 = ZERO;
- TYPE value13 = ZERO;
- TYPE value14 = ZERO;
- TYPE value15 = ZERO;
- TYPE value16 = ZERO;
- TYPE value17 = ZERO;
- TYPE value18 = ZERO;
- TYPE value19 = ZERO;
- TYPE value20 = ZERO;
- TYPE value21 = ZERO;
- TYPE value22 = ZERO;
- TYPE value23 = ZERO;
- TYPE value24 = ZERO;
- TYPE value25 = ZERO;
- TYPE value26 = ZERO;
- TYPE value27 = ZERO;
- TYPE value28 = ZERO;
- TYPE value29 = ZERO;
- TYPE value30 = ZERO;
- TYPE value31 = ZERO;
- TYPE value32 = ZERO;
- TYPE value33 = ZERO;
- TYPE value34 = ZERO;
- TYPE value35 = ZERO;
- TYPE value36 = ZERO;
- TYPE value37 = ZERO;
- TYPE value38 = ZERO;
- TYPE value39 = ZERO;
- MASK_TYPE mask;
- int eq0;
-
- while ((mask = *add_mask++) != 0)
- {
- value = *add_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 += value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 += value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 += value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 += value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 += value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 += value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 += value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 += value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 += value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 += value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 += value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 += value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 += value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 += value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 += value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 += value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 += value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 += value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 += value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 += value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 += value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 += value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 += value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 += value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 += value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 += value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 += value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 += value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 += value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 += value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 += value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 += value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 += value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 += value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 += value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 += value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 += value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 += value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 += value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 += value;
- }
-
- while ((mask = *sub_mask++) != 0)
- {
- value = *sub_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 -= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 -= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 -= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 -= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 -= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 -= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 -= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 -= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 -= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 -= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 -= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 -= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 -= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 -= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 -= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 -= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 -= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 -= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 -= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 -= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 -= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 -= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 -= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 -= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 -= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 -= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 -= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 -= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 -= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 -= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 -= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 -= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 -= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 -= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 -= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 -= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 -= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 -= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 -= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 -= value;
- }
-
- while ((mask = *mul_mask++) != 0)
- {
- value = *mul_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 *= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 *= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 *= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 *= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 *= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 *= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 *= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 *= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 *= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 *= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 *= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 *= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 *= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 *= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 *= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 *= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 *= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 *= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 *= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 *= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 *= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 *= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 *= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 *= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 *= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 *= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 *= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 *= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 *= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 *= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 *= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 *= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 *= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 *= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 *= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 *= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 *= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 *= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 *= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 *= value;
- }
-
- while ((mask = *div_mask++) != 0)
- {
- value = *div_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 /= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 /= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 /= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 /= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 /= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 /= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 /= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 /= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 /= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 /= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 /= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 /= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 /= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 /= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 /= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 /= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 /= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 /= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 /= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 /= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 /= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 /= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 /= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 /= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 /= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 /= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 /= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 /= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 /= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 /= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 /= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 /= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 /= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 /= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 /= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 /= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 /= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 /= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 /= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 /= value;
- }
-
- while ((mask = *eq0_mask++) != 0)
- {
- eq0 = 0;
-
- if ((mask & (MASK_ONE << 0)) != 0)
- eq0 |= (value00 == ZERO);
-
- if ((mask & (MASK_ONE << 1)) != 0)
- eq0 |= (value01 == ZERO);
-
- if ((mask & (MASK_ONE << 2)) != 0)
- eq0 |= (value02 == ZERO);
-
- if ((mask & (MASK_ONE << 3)) != 0)
- eq0 |= (value03 == ZERO);
-
- if ((mask & (MASK_ONE << 4)) != 0)
- eq0 |= (value04 == ZERO);
-
- if ((mask & (MASK_ONE << 5)) != 0)
- eq0 |= (value05 == ZERO);
-
- if ((mask & (MASK_ONE << 6)) != 0)
- eq0 |= (value06 == ZERO);
-
- if ((mask & (MASK_ONE << 7)) != 0)
- eq0 |= (value07 == ZERO);
-
- if ((mask & (MASK_ONE << 8)) != 0)
- eq0 |= (value08 == ZERO);
-
- if ((mask & (MASK_ONE << 9)) != 0)
- eq0 |= (value09 == ZERO);
-
- if ((mask & (MASK_ONE << 10)) != 0)
- eq0 |= (value10 == ZERO);
-
- if ((mask & (MASK_ONE << 11)) != 0)
- eq0 |= (value11 == ZERO);
-
- if ((mask & (MASK_ONE << 12)) != 0)
- eq0 |= (value12 == ZERO);
-
- if ((mask & (MASK_ONE << 13)) != 0)
- eq0 |= (value13 == ZERO);
-
- if ((mask & (MASK_ONE << 14)) != 0)
- eq0 |= (value14 == ZERO);
-
- if ((mask & (MASK_ONE << 15)) != 0)
- eq0 |= (value15 == ZERO);
-
- if ((mask & (MASK_ONE << 16)) != 0)
- eq0 |= (value16 == ZERO);
-
- if ((mask & (MASK_ONE << 17)) != 0)
- eq0 |= (value17 == ZERO);
-
- if ((mask & (MASK_ONE << 18)) != 0)
- eq0 |= (value18 == ZERO);
-
- if ((mask & (MASK_ONE << 19)) != 0)
- eq0 |= (value19 == ZERO);
-
- if ((mask & (MASK_ONE << 20)) != 0)
- eq0 |= (value20 == ZERO);
-
- if ((mask & (MASK_ONE << 21)) != 0)
- eq0 |= (value21 == ZERO);
-
- if ((mask & (MASK_ONE << 22)) != 0)
- eq0 |= (value22 == ZERO);
-
- if ((mask & (MASK_ONE << 23)) != 0)
- eq0 |= (value23 == ZERO);
-
- if ((mask & (MASK_ONE << 24)) != 0)
- eq0 |= (value24 == ZERO);
-
- if ((mask & (MASK_ONE << 25)) != 0)
- eq0 |= (value25 == ZERO);
-
- if ((mask & (MASK_ONE << 26)) != 0)
- eq0 |= (value26 == ZERO);
-
- if ((mask & (MASK_ONE << 27)) != 0)
- eq0 |= (value27 == ZERO);
-
- if ((mask & (MASK_ONE << 28)) != 0)
- eq0 |= (value28 == ZERO);
-
- if ((mask & (MASK_ONE << 29)) != 0)
- eq0 |= (value29 == ZERO);
-
- if ((mask & (MASK_ONE << 30)) != 0)
- eq0 |= (value30 == ZERO);
-
- if ((mask & (MASK_ONE << 31)) != 0)
- eq0 |= (value31 == ZERO);
-
- if ((mask & (MASK_ONE << 32)) != 0)
- eq0 |= (value32 == ZERO);
-
- if ((mask & (MASK_ONE << 33)) != 0)
- eq0 |= (value33 == ZERO);
-
- if ((mask & (MASK_ONE << 34)) != 0)
- eq0 |= (value34 == ZERO);
-
- if ((mask & (MASK_ONE << 35)) != 0)
- eq0 |= (value35 == ZERO);
-
- if ((mask & (MASK_ONE << 36)) != 0)
- eq0 |= (value36 == ZERO);
-
- if ((mask & (MASK_ONE << 37)) != 0)
- eq0 |= (value37 == ZERO);
-
- if ((mask & (MASK_ONE << 38)) != 0)
- eq0 |= (value38 == ZERO);
-
- if ((mask & (MASK_ONE << 39)) != 0)
- eq0 |= (value39 == ZERO);
-
- *eq0_ptr++ = eq0;
- }
-
- return ( value00 + value01 + value02 + value03 + value04
- + value05 + value06 + value07 + value08 + value09
- + value10 + value11 + value12 + value13 + value14
- + value15 + value16 + value17 + value18 + value19
- + value20 + value21 + value22 + value23 + value24
- + value25 + value26 + value27 + value28 + value29
- + value30 + value31 + value32 + value33 + value34
- + value35 + value36 + value37 + value38 + value39);
-}
-
-/* { dg-final { scan-assembler "fadd" } } */
-/* { dg-final { scan-assembler "fsub" } } */
-/* { dg-final { scan-assembler "fmul" } } */
-/* { dg-final { scan-assembler "fdiv" } } */
-/* { dg-final { scan-assembler "fcmpu" } } */
-/* { dg-final { scan-assembler "xsadddp" } } */
-/* { dg-final { scan-assembler "xssubdp" } } */
-/* { dg-final { scan-assembler "xsmuldp" } } */
-/* { dg-final { scan-assembler "xsdivdp" } } */
-/* { dg-final { scan-assembler "xscmpudp" } } */
Index: gcc/testsuite/gcc.target/powerpc/pr65849-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-2.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-2.c (working copy)
@@ -1,728 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* Test whether we can enable the -mupper-regs-sf with target pragmas. Make
- sure float values are allocated to the Altivec registers as well as the
- traditional FPR registers. */
-
-#ifndef TYPE
-#define TYPE float
-#endif
-
-#ifndef MASK_TYPE
-#define MASK_TYPE unsigned long long
-#endif
-
-#define MASK_ONE ((MASK_TYPE)1)
-#define ZERO ((TYPE) 0.0)
-
-#pragma GCC target ("upper-regs-sf")
-TYPE
-test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
- const MASK_TYPE *sub_mask, const TYPE *sub_values,
- const MASK_TYPE *mul_mask, const TYPE *mul_values,
- const MASK_TYPE *div_mask, const TYPE *div_values,
- const MASK_TYPE *eq0_mask, int *eq0_ptr)
-{
- TYPE value;
- TYPE value00 = ZERO;
- TYPE value01 = ZERO;
- TYPE value02 = ZERO;
- TYPE value03 = ZERO;
- TYPE value04 = ZERO;
- TYPE value05 = ZERO;
- TYPE value06 = ZERO;
- TYPE value07 = ZERO;
- TYPE value08 = ZERO;
- TYPE value09 = ZERO;
- TYPE value10 = ZERO;
- TYPE value11 = ZERO;
- TYPE value12 = ZERO;
- TYPE value13 = ZERO;
- TYPE value14 = ZERO;
- TYPE value15 = ZERO;
- TYPE value16 = ZERO;
- TYPE value17 = ZERO;
- TYPE value18 = ZERO;
- TYPE value19 = ZERO;
- TYPE value20 = ZERO;
- TYPE value21 = ZERO;
- TYPE value22 = ZERO;
- TYPE value23 = ZERO;
- TYPE value24 = ZERO;
- TYPE value25 = ZERO;
- TYPE value26 = ZERO;
- TYPE value27 = ZERO;
- TYPE value28 = ZERO;
- TYPE value29 = ZERO;
- TYPE value30 = ZERO;
- TYPE value31 = ZERO;
- TYPE value32 = ZERO;
- TYPE value33 = ZERO;
- TYPE value34 = ZERO;
- TYPE value35 = ZERO;
- TYPE value36 = ZERO;
- TYPE value37 = ZERO;
- TYPE value38 = ZERO;
- TYPE value39 = ZERO;
- MASK_TYPE mask;
- int eq0;
-
- while ((mask = *add_mask++) != 0)
- {
- value = *add_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 += value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 += value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 += value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 += value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 += value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 += value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 += value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 += value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 += value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 += value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 += value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 += value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 += value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 += value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 += value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 += value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 += value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 += value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 += value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 += value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 += value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 += value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 += value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 += value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 += value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 += value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 += value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 += value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 += value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 += value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 += value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 += value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 += value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 += value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 += value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 += value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 += value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 += value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 += value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 += value;
- }
-
- while ((mask = *sub_mask++) != 0)
- {
- value = *sub_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 -= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 -= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 -= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 -= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 -= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 -= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 -= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 -= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 -= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 -= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 -= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 -= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 -= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 -= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 -= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 -= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 -= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 -= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 -= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 -= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 -= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 -= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 -= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 -= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 -= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 -= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 -= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 -= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 -= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 -= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 -= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 -= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 -= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 -= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 -= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 -= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 -= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 -= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 -= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 -= value;
- }
-
- while ((mask = *mul_mask++) != 0)
- {
- value = *mul_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 *= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 *= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 *= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 *= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 *= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 *= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 *= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 *= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 *= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 *= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 *= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 *= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 *= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 *= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 *= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 *= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 *= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 *= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 *= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 *= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 *= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 *= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 *= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 *= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 *= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 *= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 *= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 *= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 *= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 *= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 *= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 *= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 *= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 *= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 *= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 *= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 *= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 *= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 *= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 *= value;
- }
-
- while ((mask = *div_mask++) != 0)
- {
- value = *div_values++;
-
- __asm__ (" #reg %0" : "+d" (value));
-
- if ((mask & (MASK_ONE << 0)) != 0)
- value00 /= value;
-
- if ((mask & (MASK_ONE << 1)) != 0)
- value01 /= value;
-
- if ((mask & (MASK_ONE << 2)) != 0)
- value02 /= value;
-
- if ((mask & (MASK_ONE << 3)) != 0)
- value03 /= value;
-
- if ((mask & (MASK_ONE << 4)) != 0)
- value04 /= value;
-
- if ((mask & (MASK_ONE << 5)) != 0)
- value05 /= value;
-
- if ((mask & (MASK_ONE << 6)) != 0)
- value06 /= value;
-
- if ((mask & (MASK_ONE << 7)) != 0)
- value07 /= value;
-
- if ((mask & (MASK_ONE << 8)) != 0)
- value08 /= value;
-
- if ((mask & (MASK_ONE << 9)) != 0)
- value09 /= value;
-
- if ((mask & (MASK_ONE << 10)) != 0)
- value10 /= value;
-
- if ((mask & (MASK_ONE << 11)) != 0)
- value11 /= value;
-
- if ((mask & (MASK_ONE << 12)) != 0)
- value12 /= value;
-
- if ((mask & (MASK_ONE << 13)) != 0)
- value13 /= value;
-
- if ((mask & (MASK_ONE << 14)) != 0)
- value14 /= value;
-
- if ((mask & (MASK_ONE << 15)) != 0)
- value15 /= value;
-
- if ((mask & (MASK_ONE << 16)) != 0)
- value16 /= value;
-
- if ((mask & (MASK_ONE << 17)) != 0)
- value17 /= value;
-
- if ((mask & (MASK_ONE << 18)) != 0)
- value18 /= value;
-
- if ((mask & (MASK_ONE << 19)) != 0)
- value19 /= value;
-
- if ((mask & (MASK_ONE << 20)) != 0)
- value20 /= value;
-
- if ((mask & (MASK_ONE << 21)) != 0)
- value21 /= value;
-
- if ((mask & (MASK_ONE << 22)) != 0)
- value22 /= value;
-
- if ((mask & (MASK_ONE << 23)) != 0)
- value23 /= value;
-
- if ((mask & (MASK_ONE << 24)) != 0)
- value24 /= value;
-
- if ((mask & (MASK_ONE << 25)) != 0)
- value25 /= value;
-
- if ((mask & (MASK_ONE << 26)) != 0)
- value26 /= value;
-
- if ((mask & (MASK_ONE << 27)) != 0)
- value27 /= value;
-
- if ((mask & (MASK_ONE << 28)) != 0)
- value28 /= value;
-
- if ((mask & (MASK_ONE << 29)) != 0)
- value29 /= value;
-
- if ((mask & (MASK_ONE << 30)) != 0)
- value30 /= value;
-
- if ((mask & (MASK_ONE << 31)) != 0)
- value31 /= value;
-
- if ((mask & (MASK_ONE << 32)) != 0)
- value32 /= value;
-
- if ((mask & (MASK_ONE << 33)) != 0)
- value33 /= value;
-
- if ((mask & (MASK_ONE << 34)) != 0)
- value34 /= value;
-
- if ((mask & (MASK_ONE << 35)) != 0)
- value35 /= value;
-
- if ((mask & (MASK_ONE << 36)) != 0)
- value36 /= value;
-
- if ((mask & (MASK_ONE << 37)) != 0)
- value37 /= value;
-
- if ((mask & (MASK_ONE << 38)) != 0)
- value38 /= value;
-
- if ((mask & (MASK_ONE << 39)) != 0)
- value39 /= value;
- }
-
- while ((mask = *eq0_mask++) != 0)
- {
- eq0 = 0;
-
- if ((mask & (MASK_ONE << 0)) != 0)
- eq0 |= (value00 == ZERO);
-
- if ((mask & (MASK_ONE << 1)) != 0)
- eq0 |= (value01 == ZERO);
-
- if ((mask & (MASK_ONE << 2)) != 0)
- eq0 |= (value02 == ZERO);
-
- if ((mask & (MASK_ONE << 3)) != 0)
- eq0 |= (value03 == ZERO);
-
- if ((mask & (MASK_ONE << 4)) != 0)
- eq0 |= (value04 == ZERO);
-
- if ((mask & (MASK_ONE << 5)) != 0)
- eq0 |= (value05 == ZERO);
-
- if ((mask & (MASK_ONE << 6)) != 0)
- eq0 |= (value06 == ZERO);
-
- if ((mask & (MASK_ONE << 7)) != 0)
- eq0 |= (value07 == ZERO);
-
- if ((mask & (MASK_ONE << 8)) != 0)
- eq0 |= (value08 == ZERO);
-
- if ((mask & (MASK_ONE << 9)) != 0)
- eq0 |= (value09 == ZERO);
-
- if ((mask & (MASK_ONE << 10)) != 0)
- eq0 |= (value10 == ZERO);
-
- if ((mask & (MASK_ONE << 11)) != 0)
- eq0 |= (value11 == ZERO);
-
- if ((mask & (MASK_ONE << 12)) != 0)
- eq0 |= (value12 == ZERO);
-
- if ((mask & (MASK_ONE << 13)) != 0)
- eq0 |= (value13 == ZERO);
-
- if ((mask & (MASK_ONE << 14)) != 0)
- eq0 |= (value14 == ZERO);
-
- if ((mask & (MASK_ONE << 15)) != 0)
- eq0 |= (value15 == ZERO);
-
- if ((mask & (MASK_ONE << 16)) != 0)
- eq0 |= (value16 == ZERO);
-
- if ((mask & (MASK_ONE << 17)) != 0)
- eq0 |= (value17 == ZERO);
-
- if ((mask & (MASK_ONE << 18)) != 0)
- eq0 |= (value18 == ZERO);
-
- if ((mask & (MASK_ONE << 19)) != 0)
- eq0 |= (value19 == ZERO);
-
- if ((mask & (MASK_ONE << 20)) != 0)
- eq0 |= (value20 == ZERO);
-
- if ((mask & (MASK_ONE << 21)) != 0)
- eq0 |= (value21 == ZERO);
-
- if ((mask & (MASK_ONE << 22)) != 0)
- eq0 |= (value22 == ZERO);
-
- if ((mask & (MASK_ONE << 23)) != 0)
- eq0 |= (value23 == ZERO);
-
- if ((mask & (MASK_ONE << 24)) != 0)
- eq0 |= (value24 == ZERO);
-
- if ((mask & (MASK_ONE << 25)) != 0)
- eq0 |= (value25 == ZERO);
-
- if ((mask & (MASK_ONE << 26)) != 0)
- eq0 |= (value26 == ZERO);
-
- if ((mask & (MASK_ONE << 27)) != 0)
- eq0 |= (value27 == ZERO);
-
- if ((mask & (MASK_ONE << 28)) != 0)
- eq0 |= (value28 == ZERO);
-
- if ((mask & (MASK_ONE << 29)) != 0)
- eq0 |= (value29 == ZERO);
-
- if ((mask & (MASK_ONE << 30)) != 0)
- eq0 |= (value30 == ZERO);
-
- if ((mask & (MASK_ONE << 31)) != 0)
- eq0 |= (value31 == ZERO);
-
- if ((mask & (MASK_ONE << 32)) != 0)
- eq0 |= (value32 == ZERO);
-
- if ((mask & (MASK_ONE << 33)) != 0)
- eq0 |= (value33 == ZERO);
-
- if ((mask & (MASK_ONE << 34)) != 0)
- eq0 |= (value34 == ZERO);
-
- if ((mask & (MASK_ONE << 35)) != 0)
- eq0 |= (value35 == ZERO);
-
- if ((mask & (MASK_ONE << 36)) != 0)
- eq0 |= (value36 == ZERO);
-
- if ((mask & (MASK_ONE << 37)) != 0)
- eq0 |= (value37 == ZERO);
-
- if ((mask & (MASK_ONE << 38)) != 0)
- eq0 |= (value38 == ZERO);
-
- if ((mask & (MASK_ONE << 39)) != 0)
- eq0 |= (value39 == ZERO);
-
- *eq0_ptr++ = eq0;
- }
-
- return ( value00 + value01 + value02 + value03 + value04
- + value05 + value06 + value07 + value08 + value09
- + value10 + value11 + value12 + value13 + value14
- + value15 + value16 + value17 + value18 + value19
- + value20 + value21 + value22 + value23 + value24
- + value25 + value26 + value27 + value28 + value29
- + value30 + value31 + value32 + value33 + value34
- + value35 + value36 + value37 + value38 + value39);
-}
-
-/* { dg-final { scan-assembler "fadds" } } */
-/* { dg-final { scan-assembler "fsubs" } } */
-/* { dg-final { scan-assembler "fmuls" } } */
-/* { dg-final { scan-assembler "fdivs" } } */
-/* { dg-final { scan-assembler "fcmpu" } } */
-/* { dg-final { scan-assembler "xsaddsp" } } */
-/* { dg-final { scan-assembler "xssubsp" } } */
-/* { dg-final { scan-assembler "xsmulsp" } } */
-/* { dg-final { scan-assembler "xsdivsp" } } */
-/* { dg-final { scan-assembler "xscmpudp" } } */
Index: gcc/testsuite/gcc.target/powerpc/pr71720.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr71720.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr71720.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat. */
Index: gcc/testsuite/gcc.target/powerpc/pr72853.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr72853.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr72853.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O3 -mupper-regs-df -mupper-regs-sf -funroll-loops" } */
+/* { dg-options "-mcpu=power9 -O3 -funroll-loops" } */
/* derived from 20021120-1.c, compiled for -mcpu=power9. */
Index: gcc/testsuite/gcc.target/powerpc/pr78953.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr78953.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr78953.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
#include <altivec.h>
@@ -16,4 +16,4 @@ foo (vector int *vp, int *ip)
ip[4] = vec_extract (v, 0);
}
-/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */
+/* { dg-final { scan-assembler {\mxxextractuw\M|\mvextuw[lr]x\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr79907.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr79907.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr79907.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O3 -mno-upper-regs-df" } */
+/* { dg-options "-mcpu=power8 -O3" } */
int foo (short a[], int x)
{
Index: gcc/testsuite/gcc.target/powerpc/pr80099-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-1.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-1.c (working copy)
@@ -1,12 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* PR target/80099: compiler internal error if -mno-upper-regs-sf used. */
-
-int a;
-int int_from_mem (vector float *c)
-{
- return __builtin_vec_extract (*c, a);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr80099-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-2.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-2.c (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr80099-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-3.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-3.c (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-df" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr80099-4.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-4.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-4.c (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-di" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/pr80099-5.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr80099-5.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/pr80099-5.c (working copy)
@@ -1,128 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs" } */
-
-/* PR target/80099 was an issue with -mno-upper-regs-sf. Test for all variable
- extract types with various -mno-upper-regs-* options. */
-
-double
-d_extract_arg_n (vector double v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-float
-f_extract_arg_n (vector float v, unsigned long n)
-{
- return __builtin_vec_extract (v, n);
-}
-
-long
-sl_extract_arg_n (vector long v, unsigned long n)
-{
- return (long) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ul_extract_arg_n (vector unsigned long v, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (v, n);
-}
-
-long
-si_extract_arg_n (vector int v, unsigned long n)
-{
- return (int) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-ui_extract_arg_n (vector unsigned int v, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (v, n);
-}
-
-long
-ss_extract_arg_n (vector short v, unsigned long n)
-{
- return (short) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-us_extract_arg_n (vector unsigned short v, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (v, n);
-}
-
-long
-sc_extract_arg_n (vector signed char v, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (v, n);
-}
-
-unsigned long
-uc_extract_arg_n (vector unsigned char v, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (v, n);
-}
-
-\f
-double
-d_extract_mem_n (vector double *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-float
-f_extract_mem_n (vector float *p, unsigned long n)
-{
- return __builtin_vec_extract (*p, n);
-}
-
-long
-sl_extract_mem_n (vector long *p, unsigned long n)
-{
- return (long) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ul_extract_mem_n (vector unsigned long *p, unsigned long n)
-{
- return (unsigned long) __builtin_vec_extract (*p, n);
-}
-
-long
-si_extract_mem_n (vector int *p, unsigned long n)
-{
- return (int) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-ui_extract_mem_n (vector unsigned int *p, unsigned long n)
-{
- return (unsigned int) __builtin_vec_extract (*p, n);
-}
-
-long
-ss_extract_mem_n (vector short *p, unsigned long n)
-{
- return (short) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-us_extract_mem_n (vector unsigned short *p, unsigned long n)
-{
- return (unsigned short) __builtin_vec_extract (*p, n);
-}
-
-long
-sc_extract_mem_n (vector signed char *p, unsigned long n)
-{
- return (signed char) __builtin_vec_extract (*p, n);
-}
-
-unsigned long
-uc_extract_mem_n (vector unsigned char *p, unsigned long n)
-{
- return (unsigned char) __builtin_vec_extract (*p, n);
-}
Index: gcc/testsuite/gcc.target/powerpc/upper-regs-df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/upper-regs-df.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/upper-regs-df.c (working copy)
@@ -2,10 +2,10 @@
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power7 -O2 -mupper-regs-df" } */
+/* { dg-options "-mcpu=power7 -O2" } */
-/* Test for the -mupper-regs-df option to make sure double values are allocated
- to the Altivec registers as well as the traditional FPR registers. */
+/* Test to make sure double values are allocated to the Altivec registers as
+ well as the traditional FPR registers. */
#ifndef TYPE
#define TYPE double
Index: gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c (working copy)
@@ -2,10 +2,10 @@
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
+/* { dg-options "-mcpu=power8 -O2" } */
-/* Test for the -mupper-regs-df option to make sure double values are allocated
- to the Altivec registers as well as the traditional FPR registers. */
+/* Test make sure single precision values are allocated to the Altivec
+ registers as well as the traditional FPR registers. */
#ifndef TYPE
#define TYPE float
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-1.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-1.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
#include <altivec.h>
Index: gcc/testsuite/gcc.target/powerpc/vec-init-3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-3.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-3.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector long
merge (long a, long b)
Index: gcc/testsuite/gcc.target/powerpc/vec-init-6.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-6.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-6.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
vector int
merge (int a, int b, int c, int d)
Index: gcc/testsuite/gcc.target/powerpc/vec-init-7.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-init-7.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/vec-init-7.c (working copy)
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mcpu=power8 -O2 -mupper-regs-di" } */
+/* { dg-options "-mcpu=power8 -O2" } */
vector int
splat (int a)
Index: gcc/testsuite/gcc.target/powerpc/vec-set-char.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-char.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-char.c (working copy)
@@ -3,7 +3,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector char
insert_0_0 (vector char v)
Index: gcc/testsuite/gcc.target/powerpc/vec-set-int.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-int.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-int.c (working copy)
@@ -3,7 +3,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector int
insert_0_0 (vector int v)
Index: gcc/testsuite/gcc.target/powerpc/vec-set-short.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-set-short.c (revision 250478)
+++ gcc/testsuite/gcc.target/powerpc/vec-set-short.c (working copy)
@@ -3,7 +3,7 @@
/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
vector short
insert_0_0 (vector short v)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH, cleanup] Remove PowerPC -mupper-regs-* options
2017-07-24 20:07 ` Michael Meissner
@ 2017-07-24 20:51 ` Segher Boessenkool
2017-07-24 23:40 ` [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros Michael Meissner
0 siblings, 1 reply; 19+ messages in thread
From: Segher Boessenkool @ 2017-07-24 20:51 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
On Mon, Jul 24, 2017 at 04:06:45PM -0400, Michael Meissner wrote:
> > > +/* { dg-final { scan-assembler-times {\mfctidz\M|\mxscvdpsxds\M} 2 } } */
> >
> > You could write {\m(fctidz|xscvdpsxds)\M} which may be easier to read.
> > Come to think of it, we could do e.g. {\m(lwz)\M} as well. Not sure
> > which is nicer.
> >
> > Looks good, please commit! Thanks again,
>
> I wasn't sure which form of regex (shell, grep, egrep) was used, and what
> levels of quoting was needed, so I wrote it the other way.
Neither. "man re_syntax" (or google for "tcl re_syntax" if your system
is lacking in manpages).
Since you have it inside {}, you need no quoting at all (see "man tcl")
(well, you need to take care of unmatched { and }, but only unmatched
ones).
Segher
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros
2017-07-24 20:51 ` Segher Boessenkool
@ 2017-07-24 23:40 ` Michael Meissner
2017-07-25 12:34 ` Segher Boessenkool
0 siblings, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-24 23:40 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 1492 bytes --]
This patch eliminates the TARGET_UPPER_REGS_{DF,SF} macros. The next patch
will eliminate TARGET_UPPER_REGS_DI.
I had to tune the optimization that turned load into FPR register and then move
to Altivec register (and the store equivalent) because it used
TARGET_UPPER_REGS_<MODE> to protect SFmode on power7. I split the upper
register patch for DImode because there were a few more cases (mostly involving
VSX small integer support), and I will submit the patch after this one.
As I'm posting this, the little endian power8 build has finished the bootstrap
and is beginning the test phase, and big endian power7 is on stage 2. Assuming
both systems show no regressions, is it ok to check this patch into the trunk?
As I mentioned, my next patch will eliminate TARGET_UPPER_REGS_DI. I will
probably tackle eliminating the VSX small integer option after that, and then
eliminating the ISA 3.0 d-form options.
2017-07-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok):
Eliminate TARGET_UPPER_REGS_{DF,DI} usage.
* config/rs6000/rs6000.h (TARGET_UPPER_REGS_DF): Poison macro.
(TARGET_UPPER_REGS_SF): Likewise.
* config/rs6000/rs6000.md (ALTIVEC_DFORM): Eliminate
TARGET_UPPER_REGS_{DF,SF,DI} usage in optimizing DF/SF/DI memory
references involving Altivec registers.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: cleanup.patch003b --]
[-- Type: text/plain, Size: 4118 bytes --]
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 250485)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -3216,22 +3216,12 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
if (TARGET_VSX_TIMODE)
rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
-
- if (TARGET_UPPER_REGS_DF) /* DFmode */
- {
- rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;
- }
- else
- rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS;
-
- if (TARGET_UPPER_REGS_DI) /* DImode */
- rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS;
- else
- rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS;
}
/* Add conditional constraints based on various options, to allow us to
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 250485)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -575,9 +575,11 @@ extern int rs6000_vector_align[];
and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted
these options. In order to simplify the code, define the options in terms
of the base option (vsx, power8-vector). */
-#define TARGET_UPPER_REGS_DF TARGET_VSX
+#if (GCC_VERSION >= 3000)
+#pragma GCC poison TARGET_UPPER_REGS_DF TARGET_UPPER_REGS_SF
+#endif
+
#define TARGET_UPPER_REGS_DI TARGET_VSX
-#define TARGET_UPPER_REGS_SF TARGET_P8_VECTOR
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 250485)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -691,7 +691,7 @@ (define_code_attr SMINMAX [(smin "SM
;; D-form load to FPR register & move to Altivec register
;; Move Altivec register to FPR register and store
(define_mode_iterator ALTIVEC_DFORM [DF
- SF
+ (SF "TARGET_P8_VECTOR")
(DI "TARGET_POWERPC64")])
\f
@@ -9766,7 +9766,7 @@ (define_peephole2
(match_operand:DF 1 "any_operand" ""))
(set (match_operand:DF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!TARGET_UPPER_REGS_DF
+ "!TARGET_VSX
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
@@ -9775,7 +9775,7 @@ (define_peephole2
(match_operand:SF 1 "any_operand" ""))
(set (match_operand:SF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!TARGET_UPPER_REGS_SF
+ "!TARGET_P8_VECTOR
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
@@ -13974,8 +13974,7 @@ (define_peephole2
(match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
(match_dup 1))]
- "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
- && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 3)
@@ -14011,8 +14010,7 @@ (define_peephole2
(match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
(set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
(match_dup 1))]
- "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
- && peep2_reg_dead_p (2, operands[1])"
+ "TARGET_VSX && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
[(set (match_dup 0)
(match_dup 4))
(set (match_dup 5)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros
2017-07-24 23:40 ` [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros Michael Meissner
@ 2017-07-25 12:34 ` Segher Boessenkool
2017-07-25 13:08 ` Michael Meissner
2017-07-25 13:17 ` [PATCH #3, cleanup] Remove PowerPC TARGET_UPPER_REGS_DI macro Michael Meissner
0 siblings, 2 replies; 19+ messages in thread
From: Segher Boessenkool @ 2017-07-25 12:34 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
Hi Mike,
On Mon, Jul 24, 2017 at 07:40:26PM -0400, Michael Meissner wrote:
> This patch eliminates the TARGET_UPPER_REGS_{DF,SF} macros. The next patch
> will eliminate TARGET_UPPER_REGS_DI.
>
> I had to tune the optimization that turned load into FPR register and then move
> to Altivec register (and the store equivalent) because it used
> TARGET_UPPER_REGS_<MODE> to protect SFmode on power7.
> --- gcc/config/rs6000/rs6000.md (revision 250485)
> +++ gcc/config/rs6000/rs6000.md (working copy)
> @@ -691,7 +691,7 @@ (define_code_attr SMINMAX [(smin "SM
> ;; D-form load to FPR register & move to Altivec register
> ;; Move Altivec register to FPR register and store
> (define_mode_iterator ALTIVEC_DFORM [DF
> - SF
> + (SF "TARGET_P8_VECTOR")
> (DI "TARGET_POWERPC64")])
Is that this part?
> --- gcc/config/rs6000/rs6000.c (revision 250485)
> +++ gcc/config/rs6000/rs6000.c (working copy)
> @@ -3216,22 +3216,12 @@ rs6000_init_hard_regno_mode_ok (bool glo
> rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
> rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
> rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
> + rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
> + rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
> + rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
After this all is done you can probably simplify the constraints a bit.
Looking forward to it :-)
> --- gcc/config/rs6000/rs6000.h (revision 250485)
> +++ gcc/config/rs6000/rs6000.h (working copy)
> @@ -575,9 +575,11 @@ extern int rs6000_vector_align[];
> and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted
> these options. In order to simplify the code, define the options in terms
> of the base option (vsx, power8-vector). */
> -#define TARGET_UPPER_REGS_DF TARGET_VSX
> +#if (GCC_VERSION >= 3000)
> +#pragma GCC poison TARGET_UPPER_REGS_DF TARGET_UPPER_REGS_SF
> +#endif
Why poison it? If someone accidentally slips in a new use it won't
compile anyway.
Okay for trunk with the poison removed. Thanks!
Segher
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros
2017-07-25 12:34 ` Segher Boessenkool
@ 2017-07-25 13:08 ` Michael Meissner
2017-07-25 22:21 ` Segher Boessenkool
2017-07-25 13:17 ` [PATCH #3, cleanup] Remove PowerPC TARGET_UPPER_REGS_DI macro Michael Meissner
1 sibling, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-25 13:08 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
On Tue, Jul 25, 2017 at 07:34:46AM -0500, Segher Boessenkool wrote:
> Hi Mike,
>
> On Mon, Jul 24, 2017 at 07:40:26PM -0400, Michael Meissner wrote:
> > This patch eliminates the TARGET_UPPER_REGS_{DF,SF} macros. The next patch
> > will eliminate TARGET_UPPER_REGS_DI.
> >
> > I had to tune the optimization that turned load into FPR register and then move
> > to Altivec register (and the store equivalent) because it used
> > TARGET_UPPER_REGS_<MODE> to protect SFmode on power7.
>
> > --- gcc/config/rs6000/rs6000.md (revision 250485)
> > +++ gcc/config/rs6000/rs6000.md (working copy)
> > @@ -691,7 +691,7 @@ (define_code_attr SMINMAX [(smin "SM
> > ;; D-form load to FPR register & move to Altivec register
> > ;; Move Altivec register to FPR register and store
> > (define_mode_iterator ALTIVEC_DFORM [DF
> > - SF
> > + (SF "TARGET_P8_VECTOR")
> > (DI "TARGET_POWERPC64")])
>
> Is that this part?
Yes.
> > --- gcc/config/rs6000/rs6000.c (revision 250485)
> > +++ gcc/config/rs6000/rs6000.c (working copy)
> > @@ -3216,22 +3216,12 @@ rs6000_init_hard_regno_mode_ok (bool glo
> > rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
> > rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
> > rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
> > + rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
> > + rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
> > + rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
>
> After this all is done you can probably simplify the constraints a bit.
> Looking forward to it :-)
No, we can never remove constraints, since otherwise it would break user
written asm statements.
> > --- gcc/config/rs6000/rs6000.h (revision 250485)
> > +++ gcc/config/rs6000/rs6000.h (working copy)
> > @@ -575,9 +575,11 @@ extern int rs6000_vector_align[];
> > and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted
> > these options. In order to simplify the code, define the options in terms
> > of the base option (vsx, power8-vector). */
> > -#define TARGET_UPPER_REGS_DF TARGET_VSX
> > +#if (GCC_VERSION >= 3000)
> > +#pragma GCC poison TARGET_UPPER_REGS_DF TARGET_UPPER_REGS_SF
> > +#endif
>
> Why poison it? If someone accidentally slips in a new use it won't
> compile anyway.
>
> Okay for trunk with the poison removed. Thanks!
Ok. The second patch is in make check.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH #3, cleanup] Remove PowerPC TARGET_UPPER_REGS_DI macro
2017-07-25 12:34 ` Segher Boessenkool
2017-07-25 13:08 ` Michael Meissner
@ 2017-07-25 13:17 ` Michael Meissner
2017-07-25 22:39 ` Segher Boessenkool
1 sibling, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-25 13:17 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 1155 bytes --]
This patch eliminates TARGET_UPPER_REGS_DI. I deleted the poison attribute in
patch #1. I will combine the ChangeLog and submit this patch and the previous
patch together if approved.
It bootstraps and has no regressions on big endian power7 and little endian
power8. Can I install this patch on the trunk.
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal):
Eliminate TARGET_UPPER_REGS_DI.
(rs6000_expand_vector_set): Likewise.
* config/rs6000/vsx.md (vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
* config/rs6000/rs6000.c (TARGET_UPPER_REGS_DI): Delete.
(TARGET_VEXTRACTUB): Eliminate TARGET_UPPER_REGS_DI.
(TARGET_DIRECT_MOVE_64BIT): Likewise.
* config/rs6000/rs6000.md
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(Splitters for DI constants in Altivec registers): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: cleanup.patch005b --]
[-- Type: text/plain, Size: 6243 bytes --]
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 250487)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -4637,11 +4637,11 @@ rs6000_option_override_internal (bool gl
variables through memory to do moves. SImode can be used on ISA 2.07,
while HImode and QImode require ISA 3.0. */
if (TARGET_VSX_SMALL_INTEGER
- && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR || !TARGET_UPPER_REGS_DI))
+ && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR))
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_SMALL_INTEGER)
error ("-mvsx-small-integer requires -mpower8-vector, "
- "-mupper-regs-di, and -mdirect-move");
+ "and -mdirect-move");
rs6000_isa_flags &= ~OPTION_MASK_VSX_SMALL_INTEGER;
}
@@ -7338,8 +7338,7 @@ rs6000_expand_vector_set (rtx target, rt
else if (mode == V2DImode)
insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
- else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
+ else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64)
{
if (mode == V4SImode)
insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 250485)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -3366,7 +3366,7 @@ (define_insn "vsx_set_<mode>_p9"
(match_operand:QI 3 "<VSX_EXTRACT_PREDICATE>" "n")]
UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
{
int ele = INTVAL (operands[3]);
int nunits = GET_MODE_NUNITS (<MODE>mode);
@@ -3391,7 +3391,7 @@ (define_insn_and_split "vsx_set_v4sf_p9"
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 5)
@@ -3427,7 +3427,7 @@ (define_insn_and_split "*vsx_set_v4sf_p9
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
+ && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 4)
@@ -3458,7 +3458,7 @@ (define_insn "*vsx_insert_extract_v4sf_p
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
+ && TARGET_POWERPC64
&& (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
{
int ele = INTVAL (operands[4]);
@@ -3486,8 +3486,7 @@ (define_insn_and_split "*vsx_insert_extr
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 5 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
+ && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
"#"
"&& 1"
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 250487)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -571,16 +571,6 @@ extern int rs6000_vector_align[];
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
-/* We previously had -mupper-regs-{df,di,sf} to control whether DFmode, DImode,
- and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted
- these options. In order to simplify the code, define the options in terms
- of the base option (vsx, power8-vector). */
-#if (GCC_VERSION >= 3000)
-#pragma GCC poison TARGET_UPPER_REGS_DF TARGET_UPPER_REGS_SF
-#endif
-
-#define TARGET_UPPER_REGS_DI TARGET_VSX
-
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
Enable 32-bit fcfid's on any of the switches for newer ISA machines or
XILINX. */
@@ -610,7 +600,7 @@ extern int rs6000_vector_align[];
#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
&& TARGET_POWERPC64)
#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
- && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
+ && TARGET_POWERPC64)
/* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
#define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
@@ -770,7 +760,6 @@ extern int rs6000_vector_align[];
#define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
&& TARGET_P8_VECTOR \
&& TARGET_POWERPC64 \
- && TARGET_UPPER_REGS_DI \
&& (rs6000_altivec_element_order != 2))
/* Whether the various reciprocal divide/square root estimate instructions
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 250487)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -5438,7 +5438,7 @@ (define_insn_and_split "*float<QHI:mode>
(clobber (match_scratch:DI 3 "=X,r,X"))
(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wK"))]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_UPPER_REGS_DI && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_VSX_SMALL_INTEGER"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -8664,7 +8664,7 @@ (define_split
(define_split
[(set (match_operand:DI 0 "altivec_register_operand" "")
(match_operand:DI 1 "s5bit_cint_operand" ""))]
- "TARGET_UPPER_REGS_DI && TARGET_VSX && reload_completed"
+ "TARGET_VSX && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
@@ -8686,7 +8686,7 @@ (define_split
(define_split
[(set (match_operand:INT_ISA3 0 "altivec_register_operand" "")
(match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))]
- "TARGET_UPPER_REGS_DI && TARGET_P9_VECTOR && reload_completed"
+ "TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros
2017-07-25 13:08 ` Michael Meissner
@ 2017-07-25 22:21 ` Segher Boessenkool
0 siblings, 0 replies; 19+ messages in thread
From: Segher Boessenkool @ 2017-07-25 22:21 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
On Tue, Jul 25, 2017 at 09:08:23AM -0400, Michael Meissner wrote:
> > After this all is done you can probably simplify the constraints a bit.
> > Looking forward to it :-)
>
> No, we can never remove constraints, since otherwise it would break user
> written asm statements.
As we discussed offline, some constraints make no sense for user programs
to use, and these haven't existed very long yet either, so it might be
more worthwhile than unsafe to remove them. We'll see.
Segher
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #3, cleanup] Remove PowerPC TARGET_UPPER_REGS_DI macro
2017-07-25 13:17 ` [PATCH #3, cleanup] Remove PowerPC TARGET_UPPER_REGS_DI macro Michael Meissner
@ 2017-07-25 22:39 ` Segher Boessenkool
2017-07-26 4:23 ` [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer Michael Meissner
0 siblings, 1 reply; 19+ messages in thread
From: Segher Boessenkool @ 2017-07-25 22:39 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
Hi Mike,
On Tue, Jul 25, 2017 at 09:17:25AM -0400, Michael Meissner wrote:
> This patch eliminates TARGET_UPPER_REGS_DI. I deleted the poison attribute in
> patch #1. I will combine the ChangeLog and submit this patch and the previous
> patch together if approved.
Committing the patches separately makes it easier to find the offending
one if there are problems. Not too important here though.
> It bootstraps and has no regressions on big endian power7 and little endian
> power8. Can I install this patch on the trunk.
It looks good, please commit. Thanks!
Segher
> 2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * config/rs6000/rs6000.c (rs6000_option_override_internal):
> Eliminate TARGET_UPPER_REGS_DI.
> (rs6000_expand_vector_set): Likewise.
> * config/rs6000/vsx.md (vsx_set_<mode>_p9): Likewise.
> (vsx_set_v4sf_p9): Likewise.
> (vsx_set_v4sf_p9_zero): Likewise.
> (vsx_insert_extract_v4sf_p9): Likewise.
> (vsx_insert_extract_v4sf_p9_2): Likewise.
> * config/rs6000/rs6000.c (TARGET_UPPER_REGS_DI): Delete.
> (TARGET_VEXTRACTUB): Eliminate TARGET_UPPER_REGS_DI.
> (TARGET_DIRECT_MOVE_64BIT): Likewise.
> * config/rs6000/rs6000.md
> (float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
> (Splitters for DI constants in Altivec registers): Likewise.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer
2017-07-25 22:39 ` Segher Boessenkool
@ 2017-07-26 4:23 ` Michael Meissner
2017-07-26 4:27 ` Michael Meissner
0 siblings, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-26 4:23 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
Next up, the elimination of the -mvsx-small-integer option. This patch is a
little more complex than the previous patches. The -mvsx-small-integer was set
with -mpower8-vector or -mcpu=power8, and it would enable SImode to go into
vector registers. While power7 had the instructions to support 32-bit integer
load/stores, because it didn't have direct move between the GPR and VSX
registers, it was complicating the code generation.
If the user used -mpower9-vector or -mcpu=power9, the QImode and HImode types
also would be allowed in vector registers (ISA 2.07/power8 did not have general
purpose load and store byte/halfword instructions).
Because it enables different code based on the cpu, the changes were
different. In the places that were checking for SImode, the
TARGET_VSX_SMALL_INTEGER test was replaced with TARGET_P8_VECTOR. However, in
the places that were checking for QImode/HImode, there was already a guard test
for TARGET_P9_VECTOR. In those cases, I did not add a test for
TARGET_P8_VECTOR.
I've checked this on both a big endian power8 system and a little endian power7
system, doing both bootstraps and make check. There were no regressions. Can
I check these changes into the trunk?
My next cleanup patch may be elimination of the three options for power9/ISA
3.0 d-form (register+offset) support. Another one will probably be deleting of
the direct move option (power8/ISA 2.07).
[gcc]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
-mvsx-small-integer option.
(ISA_3_0_MASKS_IEEE): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Simplify
code, only testing for DImode being allowed in non-VSX floating
point registers.
(rs6000_init_hard_regno_mode_ok): Change TARGET_VSX_SMALL_INTEGER
to TARGET_P8_VECTOR test. Remove redundant VSX test inside of
another VSX test.
(rs6000_option_override_internal): Delete -mvsx-small-integer.
(rs6000_expand_vector_set): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Delete TARGET_VSX_SMALL_INTEGER,
since TARGET_P9_VECTOR was already tested.
(rs6000_opt_masks): Remove -mvsx-small-integer.
* config/rs6000/vsx.md (vsx_extract_<mode>): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(vsx_extract_<mode>_p9): Delete TARGET_VSX_SMALL_INTEGER, since a
test for TARGET_VEXTRACTUB was used, and that uses
TARGET_P9_VECTOR.
(p9 extract splitter): Likewise.
(vsx_extract_<mode>_di_p9): Likewise.
(vsx_extract_<mode>_store_p9): Likewise.
(vsx_extract_si): Delete TARGET_VSX_SMALL_INTEGER, since a test
for TARGET_P9_VECTOR was used. Delete code that is now dead with
the elimination of TARGET_VSX_SMALL_INTEGER.
(vsx_extract_<mode>_p8): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.
(vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
* config/rs6000/rs6000.md (sign extend splitter): Change
TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test.
(floatsi<mode>2_lfiwax_mem): Likewise.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(float<QHI:mode><FP_ISA3:mode>2): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(fix_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fixuns_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fctiw<u>z_<mode>_smallint): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(splitter for loading small constants): Likewise.
[gcc/testsuite]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
option.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powerpc/vsx-himode3.c: Likewise.
* gcc.target/powerpc/vsx-qimode.c: Likewise.
* gcc.target/powerpc/vsx-qimode2.c: Likewise.
* gcc.target/powerpc/vsx-qimode3.c: Likewise.
* gcc.target/powerpc/vsx-simode.c: Likewise.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer
2017-07-26 4:23 ` [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer Michael Meissner
@ 2017-07-26 4:27 ` Michael Meissner
2017-07-26 4:28 ` Michael Meissner
2017-07-26 20:02 ` Segher Boessenkool
0 siblings, 2 replies; 19+ messages in thread
From: Michael Meissner @ 2017-07-26 4:27 UTC (permalink / raw)
To: Michael Meissner, Segher Boessenkool, GCC Patches,
David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 3834 bytes --]
I forgot to include the patch for these changes:
[gcc]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
-mvsx-small-integer option.
(ISA_3_0_MASKS_IEEE): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Simplify
code, only testing for DImode being allowed in non-VSX floating
point registers.
(rs6000_init_hard_regno_mode_ok): Change TARGET_VSX_SMALL_INTEGER
to TARGET_P8_VECTOR test. Remove redundant VSX test inside of
another VSX test.
(rs6000_option_override_internal): Delete -mvsx-small-integer.
(rs6000_expand_vector_set): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Delete TARGET_VSX_SMALL_INTEGER,
since TARGET_P9_VECTOR was already tested.
(rs6000_opt_masks): Remove -mvsx-small-integer.
* config/rs6000/vsx.md (vsx_extract_<mode>): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(vsx_extract_<mode>_p9): Delete TARGET_VSX_SMALL_INTEGER, since a
test for TARGET_VEXTRACTUB was used, and that uses
TARGET_P9_VECTOR.
(p9 extract splitter): Likewise.
(vsx_extract_<mode>_di_p9): Likewise.
(vsx_extract_<mode>_store_p9): Likewise.
(vsx_extract_si): Delete TARGET_VSX_SMALL_INTEGER, since a test
for TARGET_P9_VECTOR was used. Delete code that is now dead with
the elimination of TARGET_VSX_SMALL_INTEGER.
(vsx_extract_<mode>_p8): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.
(vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
* config/rs6000/rs6000.md (sign extend splitter): Change
TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test.
(floatsi<mode>2_lfiwax_mem): Likewise.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(float<QHI:mode><FP_ISA3:mode>2): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(fix_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fixuns_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fctiw<u>z_<mode>_smallint): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(splitter for loading small constants): Likewise.
[gcc/testsuite]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
option.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powerpc/vsx-himode3.c: Likewise.
* gcc.target/powerpc/vsx-qimode.c: Likewise.
* gcc.target/powerpc/vsx-qimode2.c: Likewise.
* gcc.target/powerpc/vsx-qimode3.c: Likewise.
* gcc.target/powerpc/vsx-simode.c: Likewise.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: cleanup.patch006b --]
[-- Type: text/plain, Size: 20845 bytes --]
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def (revision 250485)
+++ gcc/config/rs6000/rs6000-cpus.def (working copy)
@@ -55,8 +55,7 @@
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
- | OPTION_MASK_QUAD_MEMORY_ATOMIC \
- | OPTION_MASK_VSX_SMALL_INTEGER)
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
@@ -75,8 +74,7 @@
#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_VECTOR \
- | OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_VSX_SMALL_INTEGER)
+ | OPTION_MASK_DIRECT_MOVE)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
@@ -96,7 +94,6 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
| OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
@@ -152,7 +149,6 @@
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
| OPTION_MASK_VSX \
- | OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#endif
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (revision 250485)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -606,10 +606,6 @@ mfloat128-convert
Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
Enable default conversions between __float128 & long double.
-mvsx-small-integer
-Target Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags)
-Enable small integers to be in VSX registers.
-
mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
Use given stack-protector guard.
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 250508)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -2099,20 +2099,8 @@ rs6000_hard_regno_mode_ok (int regno, ma
&& FP_REGNO_P (last_regno))
return 1;
- if (GET_MODE_CLASS (mode) == MODE_INT)
- {
- if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
- return 1;
-
- if (TARGET_VSX_SMALL_INTEGER)
- {
- if (mode == SImode)
- return 1;
-
- if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
- return 1;
- }
- }
+ if (mode == DImode)
+ return 1;
if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode))
@@ -3291,7 +3279,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
/* Support small integers in VSX registers. */
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
{
rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
@@ -3446,18 +3434,14 @@ rs6000_init_hard_regno_mode_ok (bool glo
}
}
- if (TARGET_VSX)
- {
- reg_addr[DFmode].scalar_in_vmx_p = true;
- reg_addr[DImode].scalar_in_vmx_p = true;
- }
+ reg_addr[DFmode].scalar_in_vmx_p = true;
+ reg_addr[DImode].scalar_in_vmx_p = true;
if (TARGET_P8_VECTOR)
- reg_addr[SFmode].scalar_in_vmx_p = true;
-
- if (TARGET_VSX_SMALL_INTEGER)
{
+ reg_addr[SFmode].scalar_in_vmx_p = true;
reg_addr[SImode].scalar_in_vmx_p = true;
+
if (TARGET_P9_VECTOR)
{
reg_addr[HImode].scalar_in_vmx_p = true;
@@ -4632,20 +4616,6 @@ rs6000_option_override_internal (bool gl
}
}
- /* Check whether we should allow small integers into VSX registers. We
- require direct move to prevent the register allocator from having to move
- variables through memory to do moves. SImode can be used on ISA 2.07,
- while HImode and QImode require ISA 3.0. */
- if (TARGET_VSX_SMALL_INTEGER
- && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR))
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_SMALL_INTEGER)
- error ("-mvsx-small-integer requires -mpower8-vector, "
- "and -mdirect-move");
-
- rs6000_isa_flags &= ~OPTION_MASK_VSX_SMALL_INTEGER;
- }
-
/* Set long double size before the IEEE 128-bit tests. */
if (!global_options_set.x_rs6000_long_double_type_size)
{
@@ -7338,7 +7308,7 @@ rs6000_expand_vector_set (rtx target, rt
else if (mode == V2DImode)
insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
- else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64)
+ else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
{
if (mode == V4SImode)
insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
@@ -19713,7 +19683,7 @@ rs6000_secondary_reload_simple_move (enu
}
/* ISA 2.07: MTVSRWZ or MFVSRWZ. */
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
{
if (mode == SImode)
return true;
@@ -20547,7 +20517,6 @@ rs6000_preferred_reload_class (rtx x, en
/* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
a sign extend in the Altivec registers. */
if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
- && TARGET_VSX_SMALL_INTEGER
&& (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
return ALTIVEC_REGS;
}
@@ -36255,7 +36224,6 @@ static struct rs6000_opt_mask const rs60
{ "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "vsx-small-integer", OPTION_MASK_VSX_SMALL_INTEGER, false, true },
{ "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 250508)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -2938,7 +2938,7 @@ (define_expand "vsx_extract_<mode>"
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
{
/* If we have ISA 3.0, we can do a xxextractuw/vextractu{b,h}. */
- if (TARGET_VSX_SMALL_INTEGER && TARGET_P9_VECTOR)
+ if (TARGET_P9_VECTOR)
{
emit_insn (gen_vsx_extract_<mode>_p9 (operands[0], operands[1],
operands[2]));
@@ -2952,8 +2952,7 @@ (define_insn "vsx_extract_<mode>_p9"
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
(clobber (match_scratch:SI 3 "=r,X"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
{
if (which_alternative == 0)
return "#";
@@ -2983,8 +2982,7 @@ (define_split
(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand")
(parallel [(match_operand:QI 2 "const_int_operand")])))
(clobber (match_operand:SI 3 "int_reg_operand"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER && reload_completed"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB && reload_completed"
[(const_int 0)]
{
rtx op0_si = gen_rtx_REG (SImode, REGNO (operands[0]));
@@ -3009,8 +3007,7 @@ (define_insn_and_split "*vsx_extract_<mo
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
(clobber (match_scratch:SI 3 "=r,X"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 4)
@@ -3030,8 +3027,7 @@ (define_insn_and_split "*vsx_extract_<mo
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))
(clobber (match_scratch:<VS_scalar> 3 "=<VSX_EX>,&r"))
(clobber (match_scratch:SI 4 "=X,&r"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3048,8 +3044,7 @@ (define_insn_and_split "*vsx_extract_si
(match_operand:V4SI 1 "gpc_reg_operand" "wJv,wJv,wJv")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))
(clobber (match_scratch:V4SI 3 "=wJv,wJv,wJv"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT
- && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)"
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT && !TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -3067,15 +3062,7 @@ (define_insn_and_split "*vsx_extract_si
instruction. */
value = INTVAL (element);
if (value != 1)
- {
- if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER)
- {
- rtx si_tmp = gen_rtx_REG (SImode, REGNO (vec_tmp));
- emit_insn (gen_vsx_extract_v4si_p9 (si_tmp,src, element));
- }
- else
- emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element));
- }
+ emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element));
else
vec_tmp = src;
@@ -3084,13 +3071,13 @@ (define_insn_and_split "*vsx_extract_si
if (can_create_pseudo_p ())
dest = rs6000_address_for_fpconvert (dest);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp)));
else
emit_insn (gen_stfiwx (dest, gen_rtx_REG (DImode, REGNO (vec_tmp))));
}
- else if (TARGET_VSX_SMALL_INTEGER)
+ else if (TARGET_P8_VECTOR)
emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp)));
else
emit_move_insn (gen_rtx_REG (DImode, REGNO (dest)),
@@ -3108,7 +3095,7 @@ (define_insn_and_split "*vsx_extract_<m
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
(clobber (match_scratch:VSX_EXTRACT_I2 3 "=v"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)"
+ && !TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -3319,7 +3306,7 @@ (define_insn_and_split "*vsx_ext_<VSX_EX
(parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
(clobber (match_scratch:<VSX_EXTRACT_I:VS_scalar> 3 "=v"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3343,7 +3330,7 @@ (define_insn_and_split "*vsx_ext_<VSX_EX
(parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
(clobber (match_scratch:<VSX_EXTRACT_I:VS_scalar> 3 "=v"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3365,8 +3352,7 @@ (define_insn "vsx_set_<mode>_p9"
(match_operand:<VS_scalar> 2 "gpc_reg_operand" "<VSX_EX>")
(match_operand:QI 3 "<VSX_EXTRACT_PREDICATE>" "n")]
UNSPEC_VSX_SET))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
{
int ele = INTVAL (operands[3]);
int nunits = GET_MODE_NUNITS (<MODE>mode);
@@ -3390,8 +3376,7 @@ (define_insn_and_split "vsx_set_v4sf_p9"
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 5)
@@ -3426,8 +3411,7 @@ (define_insn_and_split "*vsx_set_v4sf_p9
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 4)
@@ -3457,8 +3441,7 @@ (define_insn "*vsx_insert_extract_v4sf_p
[(match_operand:QI 3 "const_0_to_3_operand" "n")]))
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
{
int ele = INTVAL (operands[4]);
@@ -3486,7 +3469,7 @@ (define_insn_and_split "*vsx_insert_extr
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 5 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64
+ && TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
"#"
"&& 1"
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 250508)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -1004,8 +1004,7 @@ (define_insn "extendsi<mode>2"
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
(sign_extend:DI (match_operand:SI 1 "altivec_register_operand")))]
- "TARGET_VSX_SMALL_INTEGER && TARGET_P8_VECTOR && !TARGET_P9_VECTOR
- && reload_completed"
+ "TARGET_P8_VECTOR && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx dest = operands[0];
@@ -5161,7 +5160,7 @@ (define_insn_and_split "floatsi<mode>2_l
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_insn (gen_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwax (operands[2], operands[1]));
@@ -5238,7 +5237,7 @@ (define_insn_and_split "floatunssi<mode>
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_insn (gen_zero_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwzx (operands[2], operands[1]));
@@ -5423,8 +5422,7 @@ (define_expand "float<QHI:mode><FP_ISA3:
(clobber (match_scratch:DI 2))
(clobber (match_scratch:DI 3))
(clobber (match_scratch:<QHI:MODE> 4))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
operands[1] = rs6000_address_for_fpconvert (operands[1]);
@@ -5437,8 +5435,7 @@ (define_insn_and_split "*float<QHI:mode>
(clobber (match_scratch:DI 2 "=wK,wi,wK"))
(clobber (match_scratch:DI 3 "=X,r,X"))
(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wK"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5477,8 +5474,7 @@ (define_expand "floatuns<QHI:mode><FP_IS
(match_operand:QHI 1 "input_operand" "")))
(clobber (match_scratch:DI 2 ""))
(clobber (match_scratch:DI 3 ""))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
operands[1] = rs6000_address_for_fpconvert (operands[1]);
@@ -5490,8 +5486,7 @@ (define_insn_and_split "*floatuns<QHI:mo
(match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z")))
(clobber (match_scratch:DI 2 "=wK,wi,wJwK"))
(clobber (match_scratch:DI 3 "=X,r,X"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5524,7 +5519,7 @@ (define_expand "fix_trunc<mode>si2"
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
"
{
- if (!TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_P8_VECTOR)
{
rtx src = force_reg (<MODE>mode, operands[1]);
@@ -5551,7 +5546,7 @@ (define_insn_and_split "fix_trunc<mode>s
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
&& TARGET_STFIWX && can_create_pseudo_p ()
- && !TARGET_VSX_SMALL_INTEGER"
+ && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5592,7 +5587,7 @@ (define_insn_and_split "fix_trunc<mode>s
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5629,8 +5624,7 @@ (define_expand "fix_trunc<SFDF:mode><QHI
[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
(fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
{
if (MEM_P (operands[0]))
operands[0] = rs6000_address_for_fpconvert (operands[0]);
@@ -5641,8 +5635,7 @@ (define_insn_and_split "*fix_trunc<SFDF:
(fix:QHI
(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
(clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5672,7 +5665,7 @@ (define_expand "fixuns_trunc<mode>si2"
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
"
{
- if (!TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_P8_VECTOR)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
@@ -5685,7 +5678,7 @@ (define_insn_and_split "fixuns_trunc<mod
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ
&& TARGET_STFIWX && can_create_pseudo_p ()
- && !TARGET_VSX_SMALL_INTEGER"
+ && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5734,8 +5727,7 @@ (define_expand "fixuns_trunc<SFDF:mode><
[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
(unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
{
if (MEM_P (operands[0]))
operands[0] = rs6000_address_for_fpconvert (operands[0]);
@@ -5746,8 +5738,7 @@ (define_insn_and_split "*fixuns_trunc<SF
(unsigned_fix:QHI
(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
(clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5777,7 +5768,7 @@ (define_insn_and_split "*fixuns_trunc<SF
(define_insn "*fctiw<u>z_<mode>_smallint"
[(set (match_operand:SI 0 "vsx_register_operand" "=d,wi")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
"@
fctiw<u>z %0,%1
xscvdp<su>xws %x0,%x1"
@@ -5789,7 +5780,7 @@ (define_insn_and_split "*fctiw<u>z_<mode
[(set (match_operand:SI 0 "memory_operand" "=Z")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
(clobber (match_scratch:SI 2 "=wa"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -6959,7 +6950,7 @@ (define_split
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
(match_operand:DI 1 "xxspltib_constant_split"))]
- "TARGET_VSX_SMALL_INTEGER && TARGET_P9_VECTOR && reload_completed"
+ "TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer
2017-07-26 4:27 ` Michael Meissner
@ 2017-07-26 4:28 ` Michael Meissner
2017-07-26 20:41 ` Segher Boessenkool
2017-07-26 20:02 ` Segher Boessenkool
1 sibling, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-26 4:28 UTC (permalink / raw)
To: Michael Meissner, Segher Boessenkool, GCC Patches,
David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 760 bytes --]
And not only the patches to the compiler, I forgot to include the testsuite
patches:
[gcc/testsuite]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
option.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powerpc/vsx-himode3.c: Likewise.
* gcc.target/powerpc/vsx-qimode.c: Likewise.
* gcc.target/powerpc/vsx-qimode2.c: Likewise.
* gcc.target/powerpc/vsx-qimode3.c: Likewise.
* gcc.target/powerpc/vsx-simode.c: Likewise.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: cleanup.patch006c --]
[-- Type: text/plain, Size: 5627 bytes --]
Index: gcc/testsuite/gcc.target/powerpc/vsx-qimode.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-qimode.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-qimode.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_d_constraint (signed char *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-himode.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-himode.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-himode.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_d_constraint (short *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-simode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-simode2.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-simode2.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
unsigned int foo (unsigned int u)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-simode3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-simode3.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-simode3.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
double load_asm_v_constraint (int *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-himode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-himode2.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-himode2.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
unsigned int foo (unsigned short u)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-himode3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-himode3.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-himode3.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_v_constraint (short *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-simode.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-simode.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-simode.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
double load_asm_d_constraint (int *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
unsigned int foo (unsigned char u)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c (revision 250549)
+++ gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c (revision 250550)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_v_constraint (signed char *p)
{
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer
2017-07-26 4:27 ` Michael Meissner
2017-07-26 4:28 ` Michael Meissner
@ 2017-07-26 20:02 ` Segher Boessenkool
2017-07-26 20:53 ` Michael Meissner
1 sibling, 1 reply; 19+ messages in thread
From: Segher Boessenkool @ 2017-07-26 20:02 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
Hi Mike,
On Wed, Jul 26, 2017 at 12:24:17AM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
> -mvsx-small-integer option.
> (ISA_3_0_MASKS_IEEE): Likewise.
> (POWERPC_MASKS): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
> @@ -2099,20 +2099,8 @@ rs6000_hard_regno_mode_ok (int regno, ma
> - if (TARGET_VSX_SMALL_INTEGER)
> - {
> - if (mode == SImode)
> - return 1;
I don't see why deleting this is correct?
> - if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
> - return 1;
And this.
The rest looks fine I think.
Segher
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer
2017-07-26 4:28 ` Michael Meissner
@ 2017-07-26 20:41 ` Segher Boessenkool
0 siblings, 0 replies; 19+ messages in thread
From: Segher Boessenkool @ 2017-07-26 20:41 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
On Wed, Jul 26, 2017 at 12:28:02AM -0400, Michael Meissner wrote:
> And not only the patches to the compiler, I forgot to include the testsuite
> patches:
>
> [gcc/testsuite]
> 2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
> option.
> * gcc.target/powerpc/vsx-himode2.c: Likewise.
> * gcc.target/powerpc/vsx-himode3.c: Likewise.
> * gcc.target/powerpc/vsx-qimode.c: Likewise.
> * gcc.target/powerpc/vsx-qimode2.c: Likewise.
> * gcc.target/powerpc/vsx-qimode3.c: Likewise.
> * gcc.target/powerpc/vsx-simode.c: Likewise.
> * gcc.target/powerpc/vsx-simode2.c: Likewise.
> * gcc.target/powerpc/vsx-simode3.c: Likewise.
These are fine, thanks!
Segher
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer
2017-07-26 20:02 ` Segher Boessenkool
@ 2017-07-26 20:53 ` Michael Meissner
2017-07-26 23:07 ` [PATCH #4, cleanup, committed] " Michael Meissner
0 siblings, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-26 20:53 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
On Wed, Jul 26, 2017 at 03:02:15PM -0500, Segher Boessenkool wrote:
> Hi Mike,
>
> On Wed, Jul 26, 2017 at 12:24:17AM -0400, Michael Meissner wrote:
> > * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
> > -mvsx-small-integer option.
> > (ISA_3_0_MASKS_IEEE): Likewise.
> > (POWERPC_MASKS): Likewise.
>
> (OTHER_VSX_VECTOR_MASKS): Likewise.
Thanks.
> > @@ -2099,20 +2099,8 @@ rs6000_hard_regno_mode_ok (int regno, ma
>
> > - if (TARGET_VSX_SMALL_INTEGER)
> > - {
> > - if (mode == SImode)
> > - return 1;
>
> I don't see why deleting this is correct?
>
> > - if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
> > - return 1;
>
> And this.
Hmmm, I was assuming that the previous test for TARGET_VSX would catch all of
the cases, but for power7, SFmode does not allow scalars in Altivec registers,
so it will fall through. Let me change it back, and add a TARGET_P8_VECTOR
test.
Thanks for catching this.
I did start a non-boostrap build on p9 to make sure everything is ok.
> The rest looks fine I think.
>
>
> Segher
>
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup, committed] Remove PowerPC -mvsx-small-integer
2017-07-26 20:53 ` Michael Meissner
@ 2017-07-26 23:07 ` Michael Meissner
2017-08-06 14:05 ` Andreas Schwab
0 siblings, 1 reply; 19+ messages in thread
From: Michael Meissner @ 2017-07-26 23:07 UTC (permalink / raw)
To: Michael Meissner, Segher Boessenkool, GCC Patches,
David Edelsohn, Bill Schmidt
[-- Attachment #1: Type: text/plain, Size: 3864 bytes --]
This is the final patch that I committed.
[gcc]
2017-07-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
-mvsx-small-integer option.
(ISA_3_0_MASKS_IEEE): Likewise.
(OTHER_VSX_VECTOR_MASKS): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Simplify
code, only testing for DImode being allowed in non-VSX floating
point registers.
(rs6000_init_hard_regno_mode_ok): Change TARGET_VSX_SMALL_INTEGER
to TARGET_P8_VECTOR test. Remove redundant VSX test inside of
another VSX test.
(rs6000_option_override_internal): Delete -mvsx-small-integer.
(rs6000_expand_vector_set): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Delete TARGET_VSX_SMALL_INTEGER,
since TARGET_P9_VECTOR was already tested.
(rs6000_opt_masks): Remove -mvsx-small-integer.
* config/rs6000/vsx.md (vsx_extract_<mode>): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(vsx_extract_<mode>_p9): Delete TARGET_VSX_SMALL_INTEGER, since a
test for TARGET_VEXTRACTUB was used, and that uses
TARGET_P9_VECTOR.
(p9 extract splitter): Likewise.
(vsx_extract_<mode>_di_p9): Likewise.
(vsx_extract_<mode>_store_p9): Likewise.
(vsx_extract_si): Delete TARGET_VSX_SMALL_INTEGER, since a test
for TARGET_P9_VECTOR was used. Delete code that is now dead with
the elimination of TARGET_VSX_SMALL_INTEGER.
(vsx_extract_<mode>_p8): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_fl_<FL_CONV:mode>): Likewise.
(vsx_ext_<VSX_EXTRACT_I:VS_scalar>_ufl_<FL_CONV:mode>): Likewise.
(vsx_set_<mode>_p9): Likewise.
(vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Likewise.
(vsx_insert_extract_v4sf_p9): Likewise.
(vsx_insert_extract_v4sf_p9_2): Likewise.
* config/rs6000/rs6000.md (sign extend splitter): Change
TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test.
(floatsi<mode>2_lfiwax_mem): Likewise.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(float<QHI:mode><FP_ISA3:mode>2): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(float<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2): Likewise.
(floatuns<QHI:mode><FP_ISA3:mode>2_internal): Likewise.
(fix_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fix_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fix_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fixuns_trunc<mode>si2): Change TARGET_VSX_SMALL_INTEGER to
TARGET_P8_VECTOR test.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fixuns_trunc<SFDF:mode><QHI:mode>2): Delete
TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was
used.
(fixuns_trunc<SFDF:mode><QHI:mode>2_internal): Likewise.
(fctiw<u>z_<mode>_smallint): Delete TARGET_VSX_SMALL_INTEGER,
since a test for TARGET_P9_VECTOR was used.
(splitter for loading small constants): Likewise.
[gcc/testsuite]
2017-07-25 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer
option.
* gcc.target/powerpc/vsx-himode2.c: Likewise.
* gcc.target/powerpc/vsx-himode3.c: Likewise.
* gcc.target/powerpc/vsx-qimode.c: Likewise.
* gcc.target/powerpc/vsx-qimode2.c: Likewise.
* gcc.target/powerpc/vsx-qimode3.c: Likewise.
* gcc.target/powerpc/vsx-simode.c: Likewise.
* gcc.target/powerpc/vsx-simode2.c: Likewise.
* gcc.target/powerpc/vsx-simode3.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: cleanup.patch007b --]
[-- Type: text/plain, Size: 26419 bytes --]
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def (revision 250594)
+++ gcc/config/rs6000/rs6000-cpus.def (working copy)
@@ -55,8 +55,7 @@
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
- | OPTION_MASK_QUAD_MEMORY_ATOMIC \
- | OPTION_MASK_VSX_SMALL_INTEGER)
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
@@ -75,8 +74,7 @@
#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_VECTOR \
- | OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_VSX_SMALL_INTEGER)
+ | OPTION_MASK_DIRECT_MOVE)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
@@ -96,7 +94,6 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
| OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
@@ -152,7 +149,6 @@
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
| OPTION_MASK_VSX \
- | OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#endif
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 250594)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -2104,14 +2104,11 @@ rs6000_hard_regno_mode_ok (int regno, ma
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_VSX_SMALL_INTEGER)
- {
- if (mode == SImode)
- return 1;
+ if (TARGET_P8_VECTOR && (mode == SImode))
+ return 1;
- if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
- return 1;
- }
+ if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
+ return 1;
}
if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
@@ -3291,7 +3288,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
/* Support small integers in VSX registers. */
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
{
rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
@@ -3446,18 +3443,14 @@ rs6000_init_hard_regno_mode_ok (bool glo
}
}
- if (TARGET_VSX)
- {
- reg_addr[DFmode].scalar_in_vmx_p = true;
- reg_addr[DImode].scalar_in_vmx_p = true;
- }
+ reg_addr[DFmode].scalar_in_vmx_p = true;
+ reg_addr[DImode].scalar_in_vmx_p = true;
if (TARGET_P8_VECTOR)
- reg_addr[SFmode].scalar_in_vmx_p = true;
-
- if (TARGET_VSX_SMALL_INTEGER)
{
+ reg_addr[SFmode].scalar_in_vmx_p = true;
reg_addr[SImode].scalar_in_vmx_p = true;
+
if (TARGET_P9_VECTOR)
{
reg_addr[HImode].scalar_in_vmx_p = true;
@@ -4632,20 +4625,6 @@ rs6000_option_override_internal (bool gl
}
}
- /* Check whether we should allow small integers into VSX registers. We
- require direct move to prevent the register allocator from having to move
- variables through memory to do moves. SImode can be used on ISA 2.07,
- while HImode and QImode require ISA 3.0. */
- if (TARGET_VSX_SMALL_INTEGER
- && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR))
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_SMALL_INTEGER)
- error ("-mvsx-small-integer requires -mpower8-vector, "
- "and -mdirect-move");
-
- rs6000_isa_flags &= ~OPTION_MASK_VSX_SMALL_INTEGER;
- }
-
/* Set long double size before the IEEE 128-bit tests. */
if (!global_options_set.x_rs6000_long_double_type_size)
{
@@ -7338,7 +7317,7 @@ rs6000_expand_vector_set (rtx target, rt
else if (mode == V2DImode)
insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
- else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64)
+ else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
{
if (mode == V4SImode)
insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
@@ -19713,7 +19692,7 @@ rs6000_secondary_reload_simple_move (enu
}
/* ISA 2.07: MTVSRWZ or MFVSRWZ. */
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
{
if (mode == SImode)
return true;
@@ -20547,7 +20526,6 @@ rs6000_preferred_reload_class (rtx x, en
/* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
a sign extend in the Altivec registers. */
if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
- && TARGET_VSX_SMALL_INTEGER
&& (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
return ALTIVEC_REGS;
}
@@ -36255,7 +36233,6 @@ static struct rs6000_opt_mask const rs60
{ "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "vsx-small-integer", OPTION_MASK_VSX_SMALL_INTEGER, false, true },
{ "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 250594)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -1004,8 +1004,7 @@ (define_insn "extendsi<mode>2"
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
(sign_extend:DI (match_operand:SI 1 "altivec_register_operand")))]
- "TARGET_VSX_SMALL_INTEGER && TARGET_P8_VECTOR && !TARGET_P9_VECTOR
- && reload_completed"
+ "TARGET_P8_VECTOR && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx dest = operands[0];
@@ -5161,7 +5160,7 @@ (define_insn_and_split "floatsi<mode>2_l
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_insn (gen_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwax (operands[2], operands[1]));
@@ -5238,7 +5237,7 @@ (define_insn_and_split "floatunssi<mode>
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_insn (gen_zero_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwzx (operands[2], operands[1]));
@@ -5423,8 +5422,7 @@ (define_expand "float<QHI:mode><FP_ISA3:
(clobber (match_scratch:DI 2))
(clobber (match_scratch:DI 3))
(clobber (match_scratch:<QHI:MODE> 4))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
operands[1] = rs6000_address_for_fpconvert (operands[1]);
@@ -5437,8 +5435,7 @@ (define_insn_and_split "*float<QHI:mode>
(clobber (match_scratch:DI 2 "=wK,wi,wK"))
(clobber (match_scratch:DI 3 "=X,r,X"))
(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wK"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5477,8 +5474,7 @@ (define_expand "floatuns<QHI:mode><FP_IS
(match_operand:QHI 1 "input_operand" "")))
(clobber (match_scratch:DI 2 ""))
(clobber (match_scratch:DI 3 ""))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
operands[1] = rs6000_address_for_fpconvert (operands[1]);
@@ -5490,8 +5486,7 @@ (define_insn_and_split "*floatuns<QHI:mo
(match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z")))
(clobber (match_scratch:DI 2 "=wK,wi,wJwK"))
(clobber (match_scratch:DI 3 "=X,r,X"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5524,7 +5519,7 @@ (define_expand "fix_trunc<mode>si2"
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
"
{
- if (!TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_P8_VECTOR)
{
rtx src = force_reg (<MODE>mode, operands[1]);
@@ -5551,7 +5546,7 @@ (define_insn_and_split "fix_trunc<mode>s
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
&& TARGET_STFIWX && can_create_pseudo_p ()
- && !TARGET_VSX_SMALL_INTEGER"
+ && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5592,7 +5587,7 @@ (define_insn_and_split "fix_trunc<mode>s
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5629,8 +5624,7 @@ (define_expand "fix_trunc<SFDF:mode><QHI
[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
(fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
{
if (MEM_P (operands[0]))
operands[0] = rs6000_address_for_fpconvert (operands[0]);
@@ -5641,8 +5635,7 @@ (define_insn_and_split "*fix_trunc<SFDF:
(fix:QHI
(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
(clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5672,7 +5665,7 @@ (define_expand "fixuns_trunc<mode>si2"
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
"
{
- if (!TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_P8_VECTOR)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
@@ -5685,7 +5678,7 @@ (define_insn_and_split "fixuns_trunc<mod
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ
&& TARGET_STFIWX && can_create_pseudo_p ()
- && !TARGET_VSX_SMALL_INTEGER"
+ && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5734,8 +5727,7 @@ (define_expand "fixuns_trunc<SFDF:mode><
[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
(unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
{
if (MEM_P (operands[0]))
operands[0] = rs6000_address_for_fpconvert (operands[0]);
@@ -5746,8 +5738,7 @@ (define_insn_and_split "*fixuns_trunc<SF
(unsigned_fix:QHI
(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
(clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5777,7 +5768,7 @@ (define_insn_and_split "*fixuns_trunc<SF
(define_insn "*fctiw<u>z_<mode>_smallint"
[(set (match_operand:SI 0 "vsx_register_operand" "=d,wi")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
"@
fctiw<u>z %0,%1
xscvdp<su>xws %x0,%x1"
@@ -5789,7 +5780,7 @@ (define_insn_and_split "*fctiw<u>z_<mode
[(set (match_operand:SI 0 "memory_operand" "=Z")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
(clobber (match_scratch:SI 2 "=wa"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -6959,7 +6950,7 @@ (define_split
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
(match_operand:DI 1 "xxspltib_constant_split"))]
- "TARGET_VSX_SMALL_INTEGER && TARGET_P9_VECTOR && reload_completed"
+ "TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (revision 250594)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -606,10 +606,6 @@ mfloat128-convert
Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
Enable default conversions between __float128 & long double.
-mvsx-small-integer
-Target Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags)
-Enable small integers to be in VSX registers.
-
mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
Use given stack-protector guard.
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 250594)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -2938,7 +2938,7 @@ (define_expand "vsx_extract_<mode>"
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
{
/* If we have ISA 3.0, we can do a xxextractuw/vextractu{b,h}. */
- if (TARGET_VSX_SMALL_INTEGER && TARGET_P9_VECTOR)
+ if (TARGET_P9_VECTOR)
{
emit_insn (gen_vsx_extract_<mode>_p9 (operands[0], operands[1],
operands[2]));
@@ -2952,8 +2952,7 @@ (define_insn "vsx_extract_<mode>_p9"
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
(clobber (match_scratch:SI 3 "=r,X"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
{
if (which_alternative == 0)
return "#";
@@ -2983,8 +2982,7 @@ (define_split
(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand")
(parallel [(match_operand:QI 2 "const_int_operand")])))
(clobber (match_operand:SI 3 "int_reg_operand"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER && reload_completed"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB && reload_completed"
[(const_int 0)]
{
rtx op0_si = gen_rtx_REG (SImode, REGNO (operands[0]));
@@ -3009,8 +3007,7 @@ (define_insn_and_split "*vsx_extract_<mo
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
(clobber (match_scratch:SI 3 "=r,X"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 4)
@@ -3030,8 +3027,7 @@ (define_insn_and_split "*vsx_extract_<mo
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))
(clobber (match_scratch:<VS_scalar> 3 "=<VSX_EX>,&r"))
(clobber (match_scratch:SI 4 "=X,&r"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3048,8 +3044,7 @@ (define_insn_and_split "*vsx_extract_si
(match_operand:V4SI 1 "gpc_reg_operand" "wJv,wJv,wJv")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))
(clobber (match_scratch:V4SI 3 "=wJv,wJv,wJv"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT
- && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)"
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT && !TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -3067,15 +3062,7 @@ (define_insn_and_split "*vsx_extract_si
instruction. */
value = INTVAL (element);
if (value != 1)
- {
- if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER)
- {
- rtx si_tmp = gen_rtx_REG (SImode, REGNO (vec_tmp));
- emit_insn (gen_vsx_extract_v4si_p9 (si_tmp,src, element));
- }
- else
- emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element));
- }
+ emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element));
else
vec_tmp = src;
@@ -3084,13 +3071,13 @@ (define_insn_and_split "*vsx_extract_si
if (can_create_pseudo_p ())
dest = rs6000_address_for_fpconvert (dest);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp)));
else
emit_insn (gen_stfiwx (dest, gen_rtx_REG (DImode, REGNO (vec_tmp))));
}
- else if (TARGET_VSX_SMALL_INTEGER)
+ else if (TARGET_P8_VECTOR)
emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp)));
else
emit_move_insn (gen_rtx_REG (DImode, REGNO (dest)),
@@ -3108,7 +3095,7 @@ (define_insn_and_split "*vsx_extract_<m
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
(clobber (match_scratch:VSX_EXTRACT_I2 3 "=v"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)"
+ && !TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -3319,7 +3306,7 @@ (define_insn_and_split "*vsx_ext_<VSX_EX
(parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
(clobber (match_scratch:<VSX_EXTRACT_I:VS_scalar> 3 "=v"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3343,7 +3330,7 @@ (define_insn_and_split "*vsx_ext_<VSX_EX
(parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
(clobber (match_scratch:<VSX_EXTRACT_I:VS_scalar> 3 "=v"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3365,8 +3352,7 @@ (define_insn "vsx_set_<mode>_p9"
(match_operand:<VS_scalar> 2 "gpc_reg_operand" "<VSX_EX>")
(match_operand:QI 3 "<VSX_EXTRACT_PREDICATE>" "n")]
UNSPEC_VSX_SET))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
{
int ele = INTVAL (operands[3]);
int nunits = GET_MODE_NUNITS (<MODE>mode);
@@ -3390,8 +3376,7 @@ (define_insn_and_split "vsx_set_v4sf_p9"
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 5)
@@ -3426,8 +3411,7 @@ (define_insn_and_split "*vsx_set_v4sf_p9
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 4)
@@ -3457,8 +3441,7 @@ (define_insn "*vsx_insert_extract_v4sf_p
[(match_operand:QI 3 "const_0_to_3_operand" "n")]))
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
{
int ele = INTVAL (operands[4]);
@@ -3486,7 +3469,7 @@ (define_insn_and_split "*vsx_insert_extr
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 5 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64
+ && TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
"#"
"&& 1"
Index: gcc/testsuite/gcc.target/powerpc/vsx-himode.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-himode.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-himode.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_d_constraint (short *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-himode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-himode2.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-himode2.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
unsigned int foo (unsigned short u)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-himode3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-himode3.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-himode3.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_v_constraint (short *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-qimode.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-qimode.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-qimode.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_d_constraint (signed char *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
unsigned int foo (unsigned char u)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_v_constraint (signed char *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-simode.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-simode.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-simode.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
double load_asm_d_constraint (int *p)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-simode2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-simode2.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-simode2.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
unsigned int foo (unsigned int u)
{
Index: gcc/testsuite/gcc.target/powerpc/vsx-simode3.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-simode3.c (revision 250594)
+++ gcc/testsuite/gcc.target/powerpc/vsx-simode3.c (working copy)
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
double load_asm_v_constraint (int *p)
{
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup, committed] Remove PowerPC -mvsx-small-integer
2017-07-26 23:07 ` [PATCH #4, cleanup, committed] " Michael Meissner
@ 2017-08-06 14:05 ` Andreas Schwab
2017-08-07 12:28 ` Segher Boessenkool
0 siblings, 1 reply; 19+ messages in thread
From: Andreas Schwab @ 2017-08-06 14:05 UTC (permalink / raw)
To: Michael Meissner
Cc: Segher Boessenkool, GCC Patches, David Edelsohn, Bill Schmidt
On BE/-m64:
FAIL: gcc.target/powerpc/loop_align.c scan-assembler .p2align 5,,31
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH #4, cleanup, committed] Remove PowerPC -mvsx-small-integer
2017-08-06 14:05 ` Andreas Schwab
@ 2017-08-07 12:28 ` Segher Boessenkool
0 siblings, 0 replies; 19+ messages in thread
From: Segher Boessenkool @ 2017-08-07 12:28 UTC (permalink / raw)
To: Andreas Schwab
Cc: Michael Meissner, GCC Patches, David Edelsohn, Bill Schmidt
On Sun, Aug 06, 2017 at 04:05:44PM +0200, Andreas Schwab wrote:
> On BE/-m64:
>
> FAIL: gcc.target/powerpc/loop_align.c scan-assembler .p2align 5,,31
Ah, see https://gcc.gnu.org/ml/gcc-testresults/2017-08/msg00382.html
(also for your earlier message). So this happens on all BE.
Segher
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2017-08-07 12:28 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-22 6:46 [PATCH, cleanup] Remove PowerPC -mupper-regs-* options Michael Meissner
2017-07-24 10:21 ` Segher Boessenkool
2017-07-24 20:07 ` Michael Meissner
2017-07-24 20:51 ` Segher Boessenkool
2017-07-24 23:40 ` [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros Michael Meissner
2017-07-25 12:34 ` Segher Boessenkool
2017-07-25 13:08 ` Michael Meissner
2017-07-25 22:21 ` Segher Boessenkool
2017-07-25 13:17 ` [PATCH #3, cleanup] Remove PowerPC TARGET_UPPER_REGS_DI macro Michael Meissner
2017-07-25 22:39 ` Segher Boessenkool
2017-07-26 4:23 ` [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer Michael Meissner
2017-07-26 4:27 ` Michael Meissner
2017-07-26 4:28 ` Michael Meissner
2017-07-26 20:41 ` Segher Boessenkool
2017-07-26 20:02 ` Segher Boessenkool
2017-07-26 20:53 ` Michael Meissner
2017-07-26 23:07 ` [PATCH #4, cleanup, committed] " Michael Meissner
2017-08-06 14:05 ` Andreas Schwab
2017-08-07 12:28 ` Segher Boessenkool
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).