From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 46259 invoked by alias); 25 Jul 2017 12:34:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 46239 invoked by uid 89); 25 Jul 2017 12:34:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.2 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,RP_MATCHES_RCVD,TVD_SUBJ_WIPE_DEBT autolearn=ham version=3.3.2 spammy=slips X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 25 Jul 2017 12:34:50 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v6PCYlnk005107; Tue, 25 Jul 2017 07:34:47 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id v6PCYkoL005104; Tue, 25 Jul 2017 07:34:46 -0500 Date: Tue, 25 Jul 2017 12:34:00 -0000 From: Segher Boessenkool To: Michael Meissner , GCC Patches , David Edelsohn , Bill Schmidt Subject: Re: [PATCH #2, cleanup] Remove PowerPC TARGET_UPPER_REGS_{DF,SF} macros Message-ID: <20170725123446.GF13471@gate.crashing.org> References: <20170722064604.GA19115@ibm-tiger.the-meissners.org> <20170724102115.GW13471@gate.crashing.org> <20170724200645.GA7617@ibm-tiger.the-meissners.org> <20170724205112.GC13471@gate.crashing.org> <20170724234025.GA9424@ibm-tiger.the-meissners.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170724234025.GA9424@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2017-07/txt/msg01543.txt.bz2 Hi Mike, On Mon, Jul 24, 2017 at 07:40:26PM -0400, Michael Meissner wrote: > This patch eliminates the TARGET_UPPER_REGS_{DF,SF} macros. The next patch > will eliminate TARGET_UPPER_REGS_DI. > > I had to tune the optimization that turned load into FPR register and then move > to Altivec register (and the store equivalent) because it used > TARGET_UPPER_REGS_ to protect SFmode on power7. > --- gcc/config/rs6000/rs6000.md (revision 250485) > +++ gcc/config/rs6000/rs6000.md (working copy) > @@ -691,7 +691,7 @@ (define_code_attr SMINMAX [(smin "SM > ;; D-form load to FPR register & move to Altivec register > ;; Move Altivec register to FPR register and store > (define_mode_iterator ALTIVEC_DFORM [DF > - SF > + (SF "TARGET_P8_VECTOR") > (DI "TARGET_POWERPC64")]) Is that this part? > --- gcc/config/rs6000/rs6000.c (revision 250485) > +++ gcc/config/rs6000/rs6000.c (working copy) > @@ -3216,22 +3216,12 @@ rs6000_init_hard_regno_mode_ok (bool glo > rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; > rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */ > rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */ > + rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */ > + rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */ > + rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */ After this all is done you can probably simplify the constraints a bit. Looking forward to it :-) > --- gcc/config/rs6000/rs6000.h (revision 250485) > +++ gcc/config/rs6000/rs6000.h (working copy) > @@ -575,9 +575,11 @@ extern int rs6000_vector_align[]; > and/or SFmode could go in the traditional Altivec registers. GCC 8.x deleted > these options. In order to simplify the code, define the options in terms > of the base option (vsx, power8-vector). */ > -#define TARGET_UPPER_REGS_DF TARGET_VSX > +#if (GCC_VERSION >= 3000) > +#pragma GCC poison TARGET_UPPER_REGS_DF TARGET_UPPER_REGS_SF > +#endif Why poison it? If someone accidentally slips in a new use it won't compile anyway. Okay for trunk with the poison removed. Thanks! Segher