From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 36264 invoked by alias); 24 Aug 2017 21:57:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 36250 invoked by uid 89); 24 Aug 2017 21:57:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy= X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 24 Aug 2017 21:57:40 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v7OLvbM3031595; Thu, 24 Aug 2017 16:57:37 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id v7OLvbZj031594; Thu, 24 Aug 2017 16:57:37 -0500 Date: Thu, 24 Aug 2017 22:26:00 -0000 From: Segher Boessenkool To: Bill Schmidt Cc: GCC Patches , David Edelsohn Subject: Re: [PATCH, rs6000] Fix PR81504 (vec_ld / vec_st bug) Message-ID: <20170824215736.GD13471@gate.crashing.org> References: <1775eb31-4830-c82f-faeb-83a880d6d593@linux.vnet.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1775eb31-4830-c82f-faeb-83a880d6d593@linux.vnet.ibm.com> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2017-08/txt/msg01478.txt.bz2 Hi! On Thu, Aug 24, 2017 at 04:04:23PM -0500, Bill Schmidt wrote: > @@ -1501,7 +1503,21 @@ recombine_lvx_pattern (rtx_insn *insn, del_info *t > to_delete[INSN_UID (swap_insn)].replace = true; > to_delete[INSN_UID (swap_insn)].replace_insn = swap_insn; > > - XEXP (mem, 0) = and_operation; > + /* However, first we must be sure that we make the > + base register from the AND operation available > + in case the register has been overwritten. Copy > + the base register to a new pseudo and use that > + as the base register of the AND operation in > + the new LVX instruction. */ > + rtx and_base = XEXP (and_operation, 0); > + rtx new_reg = gen_reg_rtx (GET_MODE (and_base)); > + rtx copy = gen_rtx_SET (new_reg, and_base); > + rtx_insn *new_insn = emit_insn_after (copy, and_insn); > + set_block_for_insn (new_insn, BLOCK_FOR_INSN (and_insn)); > + df_insn_rescan (new_insn); Are those last two lines needed? Doesn't emit_insn_after do this already? Oh, "copy" isn't an insn yet. Is it simpler if you change this? Okay with or without that change (also for 7). Thanks! Segher