From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 85381 invoked by alias); 29 Sep 2017 17:10:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 85371 invoked by uid 89); 29 Sep 2017 17:10:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Mike, rounds, Hx-languages-length:2113, H*r:8.14.1 X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 29 Sep 2017 17:10:30 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8THA9tq013038; Fri, 29 Sep 2017 12:10:11 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id v8THA7Wl013033; Fri, 29 Sep 2017 12:10:07 -0500 Date: Fri, 29 Sep 2017 17:10:00 -0000 From: Segher Boessenkool To: Michael Meissner , GCC Patches , David Edelsohn , Bill Schmidt Subject: Re: [PATCH], Add PowerPC ISA 3.0 IEEE 128-bit floating point round to odd built-in functions Message-ID: <20170929171005.GS8421@gate.crashing.org> References: <20170928223423.GA3629@ibm-tiger.the-meissners.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170928223423.GA3629@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2017-09/txt/msg01976.txt.bz2 Hi Mike, On Thu, Sep 28, 2017 at 06:34:23PM -0400, Michael Meissner wrote: > This patch addss built-in functions on PowerPC ISA 3.0 (power9) that allow the > user to access the round to odd IEEE 128-bit floating point instructions. > --- gcc/config/rs6000/rs6000.md (revision 253267) > +++ gcc/config/rs6000/rs6000.md (working copy) > @@ -14505,7 +14505,9 @@ (define_insn_and_split "truncsf2_h > "#" > "&& 1" > [(set (match_dup 2) > - (unspec:DF [(match_dup 1)] UNSPEC_ROUND_TO_ODD)) > + (unspec:DF [(float_truncate:DF > + (match_dup 1))] > + UNSPEC_ROUND_TO_ODD)) > (set (match_dup 0) > (float_truncate:SF (match_dup 2)))] > { I don't think this is correct. It says to first truncate the f128 to DF, and then round it to odd; I think you want to do the truncation with round-to-odd rounding mode already. > +(define_insn "mul3_odd" > + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > + (unspec:IEEE128 > + [(mult:IEEE128 > + (match_operand:IEEE128 1 "altivec_register_operand" "v") > + (match_operand:IEEE128 2 "altivec_register_operand" "v"))] > + UNSPEC_ROUND_TO_ODD))] > + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" > + "xsmulqpo %0,%1,%2" > + [(set_attr "type" "vecfloat") > + (set_attr "size" "128")]) Similar here (and everywhere else): it does an f128 mul, so rounding with whatever rounding mode is current, and *then* it rounds to odd. > +(define_insn "sqrt2_odd" > + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > + (unspec:IEEE128 > + [(sqrt:IEEE128 > + (match_operand:IEEE128 1 "altivec_register_operand" "v"))] > + UNSPEC_ROUND_TO_ODD))] > + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" > + "xssqrtqpo %0,%1" (One space too many here). Everything else looks fine, but that unspec thing needs fixing. Can be later, things will likely work for now, so okay for trunk. Thanks. How do other ports deal with this? Insns with a specific rounding mode? Have a separate unspec for every operation? Not very nice either :-( Segher