From: James Greenhalgh <james.greenhalgh@arm.com>
To: <gcc-patches@gcc.gnu.org>, <richard.earnshaw@arm.com>,
<marcus.shawcroft@arm.com>, <richard.sandiford@linaro.org>
Cc: <nd@arm.com>
Subject: Re: [04/nn] [AArch64] Rename the internal "Upl" constraint
Date: Tue, 31 Oct 2017 18:04:00 -0000 [thread overview]
Message-ID: <20171031180317.GD34758@arm.com> (raw)
In-Reply-To: <87inf0bu3f.fsf@linaro.org>
On Fri, Oct 27, 2017 at 02:25:56PM +0100, Richard Sandiford wrote:
> The SVE port uses the public constraints "Upl" and "Upa" to mean
> "low predicate register" and "any predicate register" respectively.
> "Upl" was already used as an internal-only constraint by the
> addition patterns, so this patch renames it to "Uaa" ("two adds
> needed").
OK.
Reviewed-By: James Greenhalgh <james.greenhalgh@arm.com>
Thanks,
James
>
>
> 2017-10-27 Richard Sandiford <richard.sandiford@linaro.org>
> Alan Hayward <alan.hayward@arm.com>
> David Sherwood <david.sherwood@arm.com>
>
> gcc/
> * config/aarch64/constraints.md (Upl): Rename to...
> (Uaa): ...this.
> * config/aarch64/aarch64.md
> (*zero_extend<SHORT:mode><GPI:mode>2_aarch64, *addsi3_aarch64_uxtw):
> Update accordingly.
>
> Index: gcc/config/aarch64/constraints.md
> ===================================================================
> --- gcc/config/aarch64/constraints.md 2017-10-27 14:06:16.159815485 +0100
> +++ gcc/config/aarch64/constraints.md 2017-10-27 14:11:54.071011147 +0100
> @@ -35,7 +35,7 @@ (define_constraint "I"
> (and (match_code "const_int")
> (match_test "aarch64_uimm12_shift (ival)")))
>
> -(define_constraint "Upl"
> +(define_constraint "Uaa"
> "@internal A constant that matches two uses of add instructions."
> (and (match_code "const_int")
> (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)")))
> Index: gcc/config/aarch64/aarch64.md
> ===================================================================
> --- gcc/config/aarch64/aarch64.md 2017-10-27 14:07:01.875769946 +0100
> +++ gcc/config/aarch64/aarch64.md 2017-10-27 14:11:54.071011147 +0100
> @@ -1562,7 +1562,7 @@ (define_insn "*add<mode>3_aarch64"
> (match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r")
> (plus:GPI
> (match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk")
> - (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))]
> + (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Uaa")))]
> ""
> "@
> add\\t%<w>0, %<w>1, %2
> @@ -1580,7 +1580,7 @@ (define_insn "*addsi3_aarch64_uxtw"
> (match_operand:DI 0 "register_operand" "=rk,rk,rk,r")
> (zero_extend:DI
> (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk")
> - (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))]
> + (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Uaa"))))]
> ""
> "@
> add\\t%w0, %w1, %2
next prev parent reply other threads:[~2017-10-31 18:03 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-27 13:22 [00/nn] AArch64 patches preparing for SVE Richard Sandiford
2017-10-27 13:23 ` [01/nn] [AArch64] Generate permute patterns using rtx builders Richard Sandiford
2017-10-31 18:02 ` James Greenhalgh
2017-11-02 9:03 ` Richard Sandiford
2017-10-27 13:25 ` [02/nn] [AArch64] Move code around Richard Sandiford
2017-10-31 18:03 ` James Greenhalgh
2017-10-27 13:26 ` [03/nn] [AArch64] Rework interface to add constant/offset routines Richard Sandiford
2017-10-30 11:03 ` Richard Sandiford
2017-11-10 15:43 ` James Greenhalgh
2017-10-27 13:27 ` [04/nn] [AArch64] Rename the internal "Upl" constraint Richard Sandiford
2017-10-31 18:04 ` James Greenhalgh [this message]
2017-10-27 13:28 ` [06/nn] [AArch64] Add an endian_lane_rtx helper routine Richard Sandiford
2017-11-02 9:55 ` James Greenhalgh
2017-10-27 13:28 ` [05/nn] [AArch64] Rewrite aarch64_simd_valid_immediate Richard Sandiford
2017-11-10 11:20 ` James Greenhalgh
2017-10-27 13:29 ` [07/nn] [AArch64] Pass number of units to aarch64_reverse_mask Richard Sandiford
2017-11-02 9:56 ` James Greenhalgh
2017-10-27 13:29 ` [08/nn] [AArch64] Pass number of units to aarch64_simd_vect_par_cnst_half Richard Sandiford
2017-11-02 9:59 ` James Greenhalgh
2017-10-27 13:30 ` [09/nn] [AArch64] Pass number of units to aarch64_expand_vec_perm(_const) Richard Sandiford
2017-11-02 10:00 ` James Greenhalgh
2017-10-27 13:31 ` [11/nn] [AArch64] Set NUM_POLY_INT_COEFFS to 2 Richard Sandiford
2018-01-05 11:27 ` PING: " Richard Sandiford
2018-01-06 17:57 ` James Greenhalgh
2018-01-06 19:03 ` Richard Sandiford
2017-10-27 13:31 ` [10/nn] [AArch64] Minor rtx costs tweak Richard Sandiford
2017-10-31 18:25 ` James Greenhalgh
2017-10-27 13:37 ` [12/nn] [AArch64] Add const_offset field to aarch64_address_info Richard Sandiford
2017-11-02 10:09 ` James Greenhalgh
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