* [PATCH][i386,AVX] Enable VBMI2 support [4/7]
@ 2017-10-24 9:10 Koval, Julia
2017-11-28 18:06 ` Kirill Yukhin
0 siblings, 1 reply; 2+ messages in thread
From: Koval, Julia @ 2017-10-24 9:10 UTC (permalink / raw)
To: GCC Patches; +Cc: Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 2577 bytes --]
Hi,
This patch enables VPSHLD instruction. The doc for isaset and instruction: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
gcc/
config/i386/avx512vbmi2intrin.h (_mm512_shldi_epi16,
_mm512_mask_shldi_epi16, _mm512_maskz_shldi_epi16, _mm512_shldi_epi32,
_mm512_mask_shldi_epi32, _mm512_maskz_shldi_epi32, _mm512_shldi_epi64,
_mm512_mask_shldi_epi64, _mm512_maskz_shldi_epi64): New intrinsics.
config/i386/avx512vbmi2vlintrin.h (_mm256_shldi_epi16,
_mm256_mask_shldi_epi16, _mm256_maskz_shldi_epi16,
_mm256_mask_shldi_epi32, _mm256_maskz_shldi_epi32, _mm256_shldi_epi32,
_mm256_mask_shldi_epi64, _mm256_maskz_shldi_epi64, _mm256_shldi_epi64,
_mm_mask_shldi_epi16, _mm_maskz_shldi_epi16, _mm_shldi_epi16,
_mm_mask_shldi_epi32, _mm_maskz_shldi_epi32, _mm_shldi_epi32,
_mm_mask_shldi_epi64, _mm_maskz_shldi_epi64, _mm_shldi_epi64): Ditto.
config/i386/i386-builtin-types.def (V32HI_FTYPE_V32HI_V32HI_INT,
V32HI_FTYPE_V32HI_V32HI_INT_V32HI_INT, V16SI_FTYPE_V16SI_V16SI_INT,
V16SI_FTYPE_V16SI_V16SI_INT_V16SI_INT,
V8DI_FTYPE_V8DI_V8DI_INT_V8DI_INT, V8SI_FTYPE_V8SI_V8SI_INT_V8SI_INT,
V16HI_FTYPE_V16HI_V16HI_INT_V16HI_INT,
V4DI_FTYPE_V4DI_V4DI_INT_V4DI_INT,
V8HI_FTYPE_V8HI_V8HI_INT_V8HI_INT,
V4SI_FTYPE_V4SI_V4SI_INT_V4SI_INT,
V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT): New types.
config/i386/i386-builtin.def (__builtin_ia32_vpshld_v32hi,
__builtin_ia32_vpshld_v32hi_mask, __builtin_ia32_vpshld_v16hi,
__builtin_ia32_vpshld_v16hi_mask, __builtin_ia32_vpshld_v8hi,
__builtin_ia32_vpshld_v8hi_mask, __builtin_ia32_vpshld_v16si,
__builtin_ia32_vpshld_v16si_mask, __builtin_ia32_vpshld_v8si,
__builtin_ia32_vpshld_v8si_mask, __builtin_ia32_vpshld_v4si,
__builtin_ia32_vpshld_v4si_mask, __builtin_ia32_vpshld_v8di,
__builtin_ia32_vpshld_v8di_mask, __builtin_ia32_vpshld_v4di,
__builtin_ia32_vpshld_v4di_mask, __builtin_ia32_vpshld_v2di,
__builtin_ia32_vpshld_v2di_mask): New builtins.
config/i386/i386.c (ix86_expand_args_builtin): Handle new types.
config/i386/sse.md (vpshld_<mode><mask_name>): New pattern.
gcc/testsuite/
gcc.target/i386/avx-1.c: Handle new intrinics.
gcc.target/i386/sse-13.c: Ditto.
gcc.target/i386/sse-23.c: Ditto.
gcc.target/i386/avx512f-vpshld-1.c: New test.
gcc.target/i386/avx512f-vpshldd-2.c: Ditto.
gcc.target/i386/avx512f-vpshldq-2.c: Ditto.
gcc.target/i386/avx512vl-vpshld-1.c: Ditto.
gcc.target/i386/avx512vl-vpshldd-2.c: Ditto.
gcc.target/i386/avx512vl-vpshldq-2.c: Ditto.
[-- Attachment #2: 0006-VPSHLD-instruction.patch --]
[-- Type: application/octet-stream, Size: 41249 bytes --]
From 05135b3b2a3c1bdfdcc6e13dac5bf622942d90ed Mon Sep 17 00:00:00 2001
From: "julia.koval" <jkoval@gkliclel201.igk.intel.com>
Date: Thu, 19 Oct 2017 12:02:26 +0200
Subject: [PATCH 06/14] VPSHLD instruction
---
gcc/config/i386/avx512vbmi2intrin.h | 108 +++++++++++
gcc/config/i386/avx512vbmi2vlintrin.h | 209 +++++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 11 ++
gcc/config/i386/i386-builtin.def | 18 ++
gcc/config/i386/i386.c | 16 ++
gcc/config/i386/sse.md | 14 ++
gcc/testsuite/gcc.target/i386/avx-1.c | 20 ++
gcc/testsuite/gcc.target/i386/avx512f-vpshld-1.c | 32 ++++
gcc/testsuite/gcc.target/i386/avx512f-vpshldd-2.c | 62 ++++++
gcc/testsuite/gcc.target/i386/avx512f-vpshldq-2.c | 62 ++++++
gcc/testsuite/gcc.target/i386/avx512vl-vpshld-1.c | 54 ++++++
gcc/testsuite/gcc.target/i386/avx512vl-vpshldd-2.c | 16 ++
gcc/testsuite/gcc.target/i386/avx512vl-vpshldq-2.c | 16 ++
gcc/testsuite/gcc.target/i386/sse-13.c | 20 ++
gcc/testsuite/gcc.target/i386/sse-23.c | 20 ++
15 files changed, 678 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshld-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshldd-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vpshldq-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshld-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshldd-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpshldq-2.c
diff --git a/gcc/config/i386/avx512vbmi2intrin.h b/gcc/config/i386/avx512vbmi2intrin.h
index aa936ce..7f6e878 100644
--- a/gcc/config/i386/avx512vbmi2intrin.h
+++ b/gcc/config/i386/avx512vbmi2intrin.h
@@ -149,6 +149,114 @@ _mm512_maskz_expandloadu_epi16 (__mmask32 __A, const void * __B)
return (__m512i) __builtin_ia32_expandloadhi512_maskz ((const __v32hi *) __B,
(__v32hi) _mm512_setzero_si512 (), (__mmask32) __A);
}
+
+#ifdef __OPTIMIZE__
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_shldi_epi16 (__m512i __A, __m512i __B, int __C)
+{
+ return (__m512i) __builtin_ia32_vpshld_v32hi ((__v32hi)__A, (__v32hi) __B,
+ __C);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_shldi_epi16 (__m512i __A, __mmask32 __B, __m512i __C, __m512i __D,
+ int __E)
+{
+ return (__m512i)__builtin_ia32_vpshld_v32hi_mask ((__v32hi)__C,
+ (__v32hi) __D, __E, (__v32hi) __A, (__mmask32)__B);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_shldi_epi16 (__mmask32 __A, __m512i __B, __m512i __C, int __D)
+{
+ return (__m512i)__builtin_ia32_vpshld_v32hi_mask ((__v32hi)__B,
+ (__v32hi) __C, __D, (__v32hi) _mm512_setzero_si512 (), (__mmask32)__A);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_shldi_epi32 (__m512i __A, __m512i __B, int __C)
+{
+ return (__m512i) __builtin_ia32_vpshld_v16si ((__v16si)__A, (__v16si) __B,
+ __C);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_shldi_epi32 (__m512i __A, __mmask16 __B, __m512i __C, __m512i __D,
+ int __E)
+{
+ return (__m512i)__builtin_ia32_vpshld_v16si_mask ((__v16si)__C,
+ (__v16si) __D, __E, (__v16si) __A, (__mmask16)__B);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_shldi_epi32 (__mmask16 __A, __m512i __B, __m512i __C, int __D)
+{
+ return (__m512i)__builtin_ia32_vpshld_v16si_mask ((__v16si)__B,
+ (__v16si) __C, __D, (__v16si) _mm512_setzero_si512 (), (__mmask16)__A);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_shldi_epi64 (__m512i __A, __m512i __B, int __C)
+{
+ return (__m512i) __builtin_ia32_vpshld_v8di ((__v8di)__A, (__v8di) __B, __C);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_shldi_epi64 (__m512i __A, __mmask8 __B, __m512i __C, __m512i __D,
+ int __E)
+{
+ return (__m512i)__builtin_ia32_vpshld_v8di_mask ((__v8di)__C, (__v8di) __D,
+ __E, (__v8di) __A, (__mmask8)__B);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_shldi_epi64 (__mmask8 __A, __m512i __B, __m512i __C, int __D)
+{
+ return (__m512i)__builtin_ia32_vpshld_v8di_mask ((__v8di)__B, (__v8di) __C,
+ __D, (__v8di) _mm512_setzero_si512 (), (__mmask8)__A);
+}
+#else
+#define _mm512_shldi_epi16(A, B, C) \
+ ((__m512i) __builtin_ia32_vpshld_v32hi ((__v32hi)(__m512i)(A), \
+ (__v32hi)(__m512i)(B),(int)(C))
+#define _mm512_mask_shldi_epi16(A, B, C, D, E) \
+ ((__m512i) __builtin_ia32_vpshld_v32hi_mask ((__v32hi)(__m512i)(C), \
+ (__v32hi)(__m512i)(D), (int)(E), (__v32hi)(__m512i)(A),(__mmask32)(B))
+#define _mm512_maskz_shldi_epi16(A, B, C, D) \
+ ((__m512i) __builtin_ia32_vpshld_v32hi_mask ((__v32hi)(__m512i)(B), \
+ (__v32hi)(__m512i)(C),(int)(D), \
+ (__v32hi)(__m512i)_mm512_setzero_si512 (), (__mmask32)(A))
+#define _mm512_shldi_epi32(A, B, C) \
+ ((__m512i) __builtin_ia32_vpshld_v16si ((__v16si)(__m512i)(A), \
+ (__v16si)(__m512i)(B),(int)(C))
+#define _mm512_mask_shldi_epi32(A, B, C, D, E) \
+ ((__m512i) __builtin_ia32_vpshld_v16si_mask ((__v16si)(__m512i)(C), \
+ (__v16si)(__m512i)(D), (int)(E), (__v16si)(__m512i)(A),(__mmask16)(B))
+#define _mm512_maskz_shldi_epi32(A, B, C, D) \
+ ((__m512i) __builtin_ia32_vpshld_v16si_mask ((__v16si)(__m512i)(B), \
+ (__v16si)(__m512i)(C),(int)(D), \
+ (__v16si)(__m512i)_mm512_setzero_si512 (), (__mmask16)(A))
+#define _mm512_shldi_epi64(A, B, C) \
+ ((__m512i) __builtin_ia32_vpshld_v8di ((__v8di)(__m512i)(A), \
+ (__v8di)(__m512i)(B),(int)(C))
+#define _mm512_mask_shldi_epi64(A, B, C, D, E) \
+ ((__m512i) __builtin_ia32_vpshld_v8di_mask ((__v8di)(__m512i)(C), \
+ (__v8di)(__m512i)(D), (int)(E), (__v8di)(__m512i)(A),(__mmask8)(B))
+#define _mm512_maskz_shldi_epi64(A, B, C, D) \
+ ((__m512i) __builtin_ia32_vpshld_v8di_mask ((__v8di)(__m512i)(B), \
+ (__v8di)(__m512i)(C),(int)(D), \
+ (__v8di)(__m512i)_mm512_setzero_si512 (), (__mmask8)(A))
+#endif
+
#ifdef __DISABLE_AVX512VBMI2BW__
#undef __DISABLE_AVX512VBMI2BW__
diff --git a/gcc/config/i386/avx512vbmi2vlintrin.h b/gcc/config/i386/avx512vbmi2vlintrin.h
index f47f3d0..f1d2aee 100644
--- a/gcc/config/i386/avx512vbmi2vlintrin.h
+++ b/gcc/config/i386/avx512vbmi2vlintrin.h
@@ -204,6 +204,215 @@ _mm256_maskz_expandloadu_epi16 (__mmask16 __A, const void * __B)
return (__m256i) __builtin_ia32_expandloadhi256_maskz ((const __v16hi *) __B,
(__v16hi) _mm256_setzero_si256 (), (__mmask16) __A);
}
+
+#ifdef __OPTIMIZE__
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_shldi_epi16 (__m256i __A, __m256i __B, int __C)
+{
+ return (__m256i) __builtin_ia32_vpshld_v16hi ((__v16hi)__A, (__v16hi) __B,
+ __C);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_shldi_epi16 (__m256i __A, __mmask16 __B, __m256i __C, __m256i __D,
+ int __E)
+{
+ return (__m256i)__builtin_ia32_vpshld_v16hi_mask ((__v16hi)__C,
+ (__v16hi) __D, __E, (__v16hi) __A, (__mmask16)__B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_shldi_epi16 (__mmask16 __A, __m256i __B, __m256i __C, int __D)
+{
+ return (__m256i)__builtin_ia32_vpshld_v16hi_mask ((__v16hi)__B,
+ (__v16hi) __C, __D, (__v16hi) _mm256_setzero_si256 (), (__mmask16)__A);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_shldi_epi32 (__m256i __A, __mmask8 __B, __m256i __C, __m256i __D,
+ int __E)
+{
+ return (__m256i)__builtin_ia32_vpshld_v8si_mask ((__v8si)__C, (__v8si) __D,
+ __E, (__v8si) __A, (__mmask8)__B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_shldi_epi32 (__mmask8 __A, __m256i __B, __m256i __C, int __D)
+{
+ return (__m256i)__builtin_ia32_vpshld_v8si_mask ((__v8si)__B, (__v8si) __C,
+ __D, (__v8si) _mm256_setzero_si256 (), (__mmask8)__A);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_shldi_epi32 (__m256i __A, __m256i __B, int __C)
+{
+ return (__m256i) __builtin_ia32_vpshld_v8si ((__v8si)__A, (__v8si) __B, __C);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_shldi_epi64 (__m256i __A, __mmask8 __B, __m256i __C, __m256i __D,
+ int __E)
+{
+ return (__m256i)__builtin_ia32_vpshld_v4di_mask ((__v4di)__C, (__v4di) __D,
+ __E, (__v4di) __A, (__mmask8)__B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_shldi_epi64 (__mmask8 __A, __m256i __B, __m256i __C, int __D)
+{
+ return (__m256i)__builtin_ia32_vpshld_v4di_mask ((__v4di)__B, (__v4di) __C,
+ __D, (__v4di) _mm256_setzero_si256 (), (__mmask8)__A);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_shldi_epi64 (__m256i __A, __m256i __B, int __C)
+{
+ return (__m256i) __builtin_ia32_vpshld_v4di ((__v4di)__A, (__v4di) __B, __C);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_shldi_epi16 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D,
+ int __E)
+{
+ return (__m128i)__builtin_ia32_vpshld_v8hi_mask ((__v8hi)__C, (__v8hi) __D,
+ __E, (__v8hi) __A, (__mmask8)__B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_shldi_epi16 (__mmask8 __A, __m128i __B, __m128i __C, int __D)
+{
+ return (__m128i)__builtin_ia32_vpshld_v8hi_mask ((__v8hi)__B, (__v8hi) __C,
+ __D, (__v8hi) _mm_setzero_si128 (), (__mmask8)__A);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_shldi_epi16 (__m128i __A, __m128i __B, int __C)
+{
+ return (__m128i) __builtin_ia32_vpshld_v8hi ((__v8hi)__A, (__v8hi) __B, __C);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_shldi_epi32 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D,
+ int __E)
+{
+ return (__m128i)__builtin_ia32_vpshld_v4si_mask ((__v4si)__C, (__v4si) __D,
+ __E, (__v4si) __A, (__mmask8)__B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_shldi_epi32 (__mmask8 __A, __m128i __B, __m128i __C, int __D)
+{
+ return (__m128i)__builtin_ia32_vpshld_v4si_mask ((__v4si)__B, (__v4si) __C,
+ __D, (__v4si) _mm_setzero_si128 (), (__mmask8)__A);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_shldi_epi32 (__m128i __A, __m128i __B, int __C)
+{
+ return (__m128i) __builtin_ia32_vpshld_v4si ((__v4si)__A, (__v4si) __B, __C);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_shldi_epi64 (__m128i __A, __mmask8 __B, __m128i __C, __m128i __D,
+ int __E)
+{
+ return (__m128i)__builtin_ia32_vpshld_v2di_mask ((__v2di)__C, (__v2di) __D,
+ __E, (__v2di) __A, (__mmask8)__B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_shldi_epi64 (__mmask8 __A, __m128i __B, __m128i __C, int __D)
+{
+ return (__m128i)__builtin_ia32_vpshld_v2di_mask ((__v2di)__B, (__v2di) __C,
+ __D, (__v2di) _mm_setzero_si128 (), (__mmask8)__A);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_shldi_epi64 (__m128i __A, __m128i __B, int __C)
+{
+ return (__m128i) __builtin_ia32_vpshld_v2di ((__v2di)__A, (__v2di) __B, __C);
+}
+#else
+#define _mm256_shldi_epi16(A, B, C) \
+ ((__m256i) __builtin_ia32_vpshld_v16hi ((__v16hi)(__m256i)(A), \
+ (__v16hi)(__m256i)(B),(int)(C))
+#define _mm256_mask_shldi_epi16(A, B, C, D, E) \
+ ((__m256i) __builtin_ia32_vpshld_v16hi_mask ((__v16hi)(__m256i)(C), \
+ (__v16hi)(__m256i)(D), (int)(E), (__v16hi)(__m256i)(A),(__mmask16)(B))
+#define _mm256_maskz_shldi_epi16(A, B, C, D) \
+ ((__m256i) __builtin_ia32_vpshld_v16hi_mask ((__v16hi)(__m256i)(B), \
+ (__v16hi)(__m256i)(C),(int)(D), \
+ (__v16hi)(__m256i)_mm256_setzero_si256 (), (__mmask16)(A))
+#define _mm256_shldi_epi32(A, B, C) \
+ ((__m256i) __builtin_ia32_vpshld_v8si ((__v8si)(__m256i)(A), \
+ (__v8si)(__m256i)(B),(int)(C))
+#define _mm256_mask_shldi_epi32(A, B, C, D, E) \
+ ((__m256i) __builtin_ia32_vpshld_v8si_mask ((__v8si)(__m256i)(C), \
+ (__v8si)(__m256i)(D), (int)(E), (__v8si)(__m256i)(A),(__mmask8)(B))
+#define _mm256_maskz_shldi_epi32(A, B, C, D) \
+ ((__m256i) __builtin_ia32_vpshld_v8si_mask ((__v8si)(__m256i)(B), \
+ (__v8si)(__m256i)(C),(int)(D), \
+ (__v8si)(__m256i)_mm256_setzero_si256 (), (__mmask8)(A))
+#define _mm256_shldi_epi64(A, B, C) \
+ ((__m256i) __builtin_ia32_vpshld_v4di ((__v4di)(__m256i)(A), \
+ (__v4di)(__m256i)(B),(int)(C))
+#define _mm256_mask_shldi_epi64(A, B, C, D, E) \
+ ((__m256i) __builtin_ia32_vpshld_v4di_mask ((__v4di)(__m256i)(C), \
+ (__v4di)(__m256i)(D), (int)(E), (__v4di)(__m256i)(A),(__mmask8)(B))
+#define _mm256_maskz_shldi_epi64(A, B, C, D) \
+ ((__m256i) __builtin_ia32_vpshld_v4di_mask ((__v4di)(__m256i)(B), \
+ (__v4di)(__m256i)(C),(int)(D), \
+ (__v4di)(__m256i)_mm256_setzero_si256 (), (__mmask8)(A))
+#define _mm_shldi_epi16(A, B, C) \
+ ((__m128i) __builtin_ia32_vpshld_v8hi ((__v8hi)(__m128i)(A), \
+ (__v8hi)(__m128i)(B),(int)(C))
+#define _mm_mask_shldi_epi16(A, B, C, D, E) \
+ ((__m128i) __builtin_ia32_vpshld_v8hi_mask ((__v8hi)(__m128i)(C), \
+ (__v8hi)(__m128i)(D), (int)(E), (__v8hi)(__m128i)(A),(__mmask8)(B))
+#define _mm_maskz_shldi_epi16(A, B, C, D) \
+ ((__m128i) __builtin_ia32_vpshld_v8hi_mask ((__v8hi)(__m128i)(B), \
+ (__v8hi)(__m128i)(C),(int)(D), \
+ (__v8hi)(__m128i)_mm_setzero_si128 (), (__mmask8)(A))
+#define _mm_shldi_epi32(A, B, C) \
+ ((__m128i) __builtin_ia32_vpshld_v4si ((__v4si)(__m128i)(A), \
+ (__v4si)(__m128i)(B),(int)(C))
+#define _mm_mask_shldi_epi32(A, B, C, D, E) \
+ ((__m128i) __builtin_ia32_vpshld_v4si_mask ((__v4si)(__m128i)(C), \
+ (__v4si)(__m128i)(D), (int)(E), (__v4si)(__m128i)(A),(__mmask16)(B))
+#define _mm_maskz_shldi_epi32(A, B, C, D) \
+ ((__m128i) __builtin_ia32_vpshld_v4si_mask ((__v4si)(__m128i)(B), \
+ (__v4si)(__m128i)(C),(int)(D), \
+ (__v4si)(__m128i)_mm_setzero_si128 (), (__mmask8)(A))
+#define _mm_shldi_epi64(A, B, C) \
+ ((__m128i) __builtin_ia32_vpshld_v2di ((__v2di)(__m128i)(A), \
+ (__v2di)(__m128i)(B),(int)(C))
+#define _mm_mask_shldi_epi64(A, B, C, D, E) \
+ ((__m128i) __builtin_ia32_vpshld_v2di_mask ((__v2di)(__m128i)(C), \
+ (__v2di)(__m128i)(D), (int)(E), (__v2di)(__m128i)(A),(__mmask8)(B))
+#define _mm_maskz_shldi_epi64(A, B, C, D) \
+ ((__m128i) __builtin_ia32_vpshld_v2di_mask ((__v2di)(__m128i)(B), \
+ (__v2di)(__m128i)(C),(int)(D), \
+ (__v2di)(__m128i)_mm_setzero_si128 (), (__mmask8)(A))
+#endif
+
#ifdef __DISABLE_AVX512VBMI2VL__
#undef __DISABLE_AVX512VBMI2VL__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index 48562d0..c896565 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1226,3 +1226,14 @@ DEF_FUNCTION_TYPE (V32QI, PCV32QI, V32QI, USI)
DEF_FUNCTION_TYPE (V16QI, PCV16QI, V16QI, UHI)
DEF_FUNCTION_TYPE (V16HI, PCV16HI, V16HI, UHI)
DEF_FUNCTION_TYPE (V8HI, PCV8HI, V8HI, UQI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, INT)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, INT, V32HI, INT)
+DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, INT)
+DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, INT, V16SI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, INT)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, INT, V16HI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT, V8SI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, INT)
+DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, INT, V8HI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT, V4SI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, INT)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 26cb9f6..48dda54 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -2608,6 +2608,24 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, CODE_FOR_expandv1
BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, CODE_FOR_expandv16hi_maskz, "__builtin_ia32_expandhi256_maskz", IX86_BUILTIN_PEXPANDW256Z, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, CODE_FOR_expandv8hi_mask, "__builtin_ia32_expandhi128_mask", IX86_BUILTIN_PEXPANDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI)
BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, CODE_FOR_expandv8hi_maskz, "__builtin_ia32_expandhi128_maskz", IX86_BUILTIN_PEXPANDW128Z, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v32hi, "__builtin_ia32_vpshld_v32hi", IX86_BUILTIN_VPSHLDV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v32hi_mask, "__builtin_ia32_vpshld_v32hi_mask", IX86_BUILTIN_VPSHLDV32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_INT_V32HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16hi, "__builtin_ia32_vpshld_v16hi", IX86_BUILTIN_VPSHLDV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16hi_mask, "__builtin_ia32_vpshld_v16hi_mask", IX86_BUILTIN_VPSHLDV16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT_V16HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8hi, "__builtin_ia32_vpshld_v8hi", IX86_BUILTIN_VPSHLDV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8hi_mask, "__builtin_ia32_vpshld_v8hi_mask", IX86_BUILTIN_VPSHLDV8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT_V8HI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16si, "__builtin_ia32_vpshld_v16si", IX86_BUILTIN_VPSHLDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v16si_mask, "__builtin_ia32_vpshld_v16si_mask", IX86_BUILTIN_VPSHLDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8si, "__builtin_ia32_vpshld_v8si", IX86_BUILTIN_VPSHLDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8si_mask, "__builtin_ia32_vpshld_v8si_mask", IX86_BUILTIN_VPSHLDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4si, "__builtin_ia32_vpshld_v4si", IX86_BUILTIN_VPSHLDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4si_mask, "__builtin_ia32_vpshld_v4si_mask", IX86_BUILTIN_VPSHLDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8di, "__builtin_ia32_vpshld_v8di", IX86_BUILTIN_VPSHLDV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v8di_mask, "__builtin_ia32_vpshld_v8di_mask", IX86_BUILTIN_VPSHLDV8DI_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4di, "__builtin_ia32_vpshld_v4di", IX86_BUILTIN_VPSHLDV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v4di_mask, "__builtin_ia32_vpshld_v4di_mask", IX86_BUILTIN_VPSHLDV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v2di, "__builtin_ia32_vpshld_v2di", IX86_BUILTIN_VPSHLDV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT)
+BDESC (OPTION_MASK_ISA_AVX512VBMI2, CODE_FOR_vpshld_v2di_mask, "__builtin_ia32_vpshld_v2di_mask", IX86_BUILTIN_VPSHLDV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT)
BDESC_END (ARGS2, SPECIAL_ARGS2)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 900e5aa..dee6e7e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -33698,6 +33698,9 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case UQI_FTYPE_V4SF_V4SF_INT:
case UHI_FTYPE_V16SI_V16SI_INT:
case UHI_FTYPE_V16SF_V16SF_INT:
+ case V32HI_FTYPE_V32HI_V32HI_INT:
+ case V16SI_FTYPE_V16SI_V16SI_INT:
+ case V8DI_FTYPE_V8DI_V8DI_INT:
nargs = 3;
nargs_constant = 1;
break;
@@ -33925,6 +33928,19 @@ ix86_expand_args_builtin (const struct builtin_description *d,
mask_pos = 1;
nargs_constant = 1;
break;
+ case V32HI_FTYPE_V32HI_V32HI_INT_V32HI_INT:
+ case V16SI_FTYPE_V16SI_V16SI_INT_V16SI_INT:
+ case V8DI_FTYPE_V8DI_V8DI_INT_V8DI_INT:
+ case V16HI_FTYPE_V16HI_V16HI_INT_V16HI_INT:
+ case V8SI_FTYPE_V8SI_V8SI_INT_V8SI_INT:
+ case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_INT:
+ case V8HI_FTYPE_V8HI_V8HI_INT_V8HI_INT:
+ case V4SI_FTYPE_V4SI_V4SI_INT_V4SI_INT:
+ case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_INT:
+ nargs = 5;
+ mask_pos = 1;
+ nargs_constant = 2;
+ break;
default:
gcc_unreachable ();
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b24f26f..5eedfaf 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -157,6 +157,9 @@
UNSPEC_VP4FNMADD
UNSPEC_VP4DPWSSD
UNSPEC_VP4DPWSSDS
+
+ ;; For AVX512VBMI2 support
+ UNSPEC_VPSHLD
])
(define_c_enum "unspecv" [
@@ -20224,3 +20227,14 @@
])]
"TARGET_SSE && TARGET_64BIT"
"jmp\t%P1")
+
+(define_insn "vpshld_<mode><mask_name>"
+ [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
+ (unspec:VI248_VLBW
+ [(match_operand:VI248_VLBW 1 "register_operand" "v")
+ (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
+ (match_operand:SI 3 "const_0_to_255_operand" "n")
+] UNSPEC_VPSHLD))]
+ "TARGET_AVX512VBMI2"
+ "vpshld<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
+ [(set_attr ("prefix") ("evex"))])
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c
index d03625b..62674d1 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -603,6 +603,26 @@
#define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D)
#define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D)
+/* avx512vbmi2intrin.h */
+#define __builtin_ia32_vpshld_v32hi(A, B, C) __builtin_ia32_vpshld_v32hi(A, B, 1)
+#define __builtin_ia32_vpshld_v32hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v32hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v16si(A, B, C) __builtin_ia32_vpshld_v16si(A, B, 1)
+#define __builtin_ia32_vpshld_v16si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v16si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8di(A, B, C) __builtin_ia32_vpshld_v8di(A, B, 1)
+#define __builtin_ia32_vpshld_v8di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8di_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v16hi(A, B, C) __builtin_ia32_vpshld_v16hi(A, B, 1)
+#define __builtin_ia32_vpshld_v16hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v16hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8si(A, B, C) __builtin_ia32_vpshld_v8si(A, B, 1)
+#define __builtin_ia32_vpshld_v8si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v4di(A, B, C) __builtin_ia32_vpshld_v4di(A, B, 1)
+#define __builtin_ia32_vpshld_v4di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v4di_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8hi(A, B, C) __builtin_ia32_vpshld_v8hi(A, B, 1)
+#define __builtin_ia32_vpshld_v8hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v4si(A, B, C) __builtin_ia32_vpshld_v4si(A, B, 1)
+#define __builtin_ia32_vpshld_v4si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v4si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v2di(A, B, C) __builtin_ia32_vpshld_v2di(A, B, 1)
+#define __builtin_ia32_vpshld_v2di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v2di_mask(A, B, 1, D, E)
+
#include <wmmintrin.h>
#include <immintrin.h>
#include <mm3dnow.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshld-1.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshld-1.c
new file mode 100644
index 0000000..f465ce2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshld-1.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -mavx512vbmi2 -mavx512bw -O2" } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x,y;
+volatile __mmask32 m;
+
+void extern
+avx512f_test (void)
+{
+ x = _mm512_shldi_epi16 (x, y, 3);
+ x = _mm512_maskz_shldi_epi16 (m, x, y, 3);
+ x = _mm512_mask_shldi_epi16 (x, m, y, x, 3);
+
+ x = _mm512_shldi_epi32 (x, y, 3);
+ x = _mm512_maskz_shldi_epi32 (m, x, y, 3);
+ x = _mm512_mask_shldi_epi32 (x, m, y, x, 3);
+
+ x = _mm512_shldi_epi64 (x, y, 3);
+ x = _mm512_maskz_shldi_epi64 (m, x, y, 3);
+ x = _mm512_mask_shldi_epi64 (x, m, y, x, 3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshldd-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshldd-2.c
new file mode 100644
index 0000000..5ddf493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshldd-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mavx512vbmi2 -mavx512bw" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512F
+
+#define AVX512VBMI2
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *r, int *dst, int *s1, int *s2, int imm)
+{
+ int i;
+ for (i = 0; i < SIZE; i++)
+ {
+ r[i] = (s1[i] << (imm & 31)) | (s2[i] >> (32 - (imm & 31)));
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ int res_ref[SIZE];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 1 + i;
+ src2.a[i] = 2 + 2*i;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ {
+ res1.a[i] = DEFAULT_VALUE;
+ res2.a[i] = DEFAULT_VALUE;
+ res3.a[i] = DEFAULT_VALUE;
+ }
+
+ CALC (res_ref, res1.a, src1.a, src2.a, DEFAULT_VALUE);
+
+ res1.x = INTRINSIC (_shldi_epi32) (src1.x, src2.x, DEFAULT_VALUE);
+ res2.x = INTRINSIC (_mask_shldi_epi32) (res2.x, mask, src1.x, src2.x, DEFAULT_VALUE);
+ res3.x = INTRINSIC (_maskz_shldi_epi32) (mask, src1.x, src2.x, DEFAULT_VALUE);
+
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_d) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_d) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vpshldq-2.c b/gcc/testsuite/gcc.target/i386/avx512f-vpshldq-2.c
new file mode 100644
index 0000000..0377aaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-vpshldq-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mavx512vbmi2 -mavx512bw" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512F
+
+#define AVX512VBMI2
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *r, long long *dst, long long *s1, long long *s2, long long imm)
+{
+ int i;
+ for (i = 0; i < SIZE; i++)
+ {
+ r[i] = (s1[i] << (imm & 63)) | (s2[i] >> (64 - (imm & 63)));
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ long long res_ref[SIZE];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 1 + i;
+ src2.a[i] = 2 + 2*i;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ {
+ res1.a[i] = DEFAULT_VALUE;
+ res2.a[i] = DEFAULT_VALUE;
+ res3.a[i] = DEFAULT_VALUE;
+ }
+
+ CALC (res_ref, res1.a, src1.a, src2.a, DEFAULT_VALUE);
+
+ res1.x = INTRINSIC (_shldi_epi64) (src1.x, src2.x, DEFAULT_VALUE);
+ res2.x = INTRINSIC (_mask_shldi_epi64) (res2.x, mask, src1.x, src2.x, DEFAULT_VALUE);
+ res3.x = INTRINSIC (_maskz_shldi_epi64) (mask, src1.x, src2.x, DEFAULT_VALUE);
+
+ if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_q) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_q) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshld-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshld-1.c
new file mode 100644
index 0000000..fd34f2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshld-1.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -mavx512vbmi2 -O2" } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldw\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldd\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpshldq\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i x,y;
+volatile __m128i z1,z2;
+volatile __mmask32 m;
+
+void extern
+avx512f_test (void)
+{
+ x = _mm256_shldi_epi16 (x, y, 3);
+ x = _mm256_maskz_shldi_epi16 (m, x, y, 3);
+ x = _mm256_mask_shldi_epi16 (x, m, y, x, 3);
+
+ x = _mm256_shldi_epi32 (x, y, 3);
+ x = _mm256_maskz_shldi_epi32 (m, x, y, 3);
+ x = _mm256_mask_shldi_epi32 (x, m, y, x, 3);
+
+ x = _mm256_shldi_epi64 (x, y, 3);
+ x = _mm256_maskz_shldi_epi64 (m, x, y, 3);
+ x = _mm256_mask_shldi_epi64 (x, m, y, x, 3);
+
+ z1 = _mm_shldi_epi16 (z1, z2, 3);
+ z1 = _mm_maskz_shldi_epi16 (m, z1, z2, 3);
+ z1 = _mm_mask_shldi_epi16 (z1, m, z2, z1, 3);
+
+ z1 = _mm_shldi_epi32 (z1, z2, 3);
+ z1 = _mm_maskz_shldi_epi32 (m, z1, z2, 3);
+ z1 = _mm_mask_shldi_epi32 (z1, m, z2, z1, 3);
+
+ z1 = _mm_shldi_epi64 (z1, z2, 3);
+ z1 = _mm_maskz_shldi_epi64 (m, z1, z2, 3);
+ z1 = _mm_mask_shldi_epi64 (z1, m, z2, z1, 3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshldd-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshldd-2.c
new file mode 100644
index 0000000..d47e4e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshldd-2.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512vbmi2 -mavx512bw" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpshldd-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpshldd-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshldq-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshldq-2.c
new file mode 100644
index 0000000..7a5575e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshldq-2.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512vbmi2 -mavx512bw" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpshldq-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpshldq-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index 7ab2223..650579f 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -620,4 +620,24 @@
#define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D)
#define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D)
+/* avx512vbmi2intrin.h */
+#define __builtin_ia32_vpshld_v32hi(A, B, C) __builtin_ia32_vpshld_v32hi(A, B, 1)
+#define __builtin_ia32_vpshld_v32hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v32hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v16si(A, B, C) __builtin_ia32_vpshld_v16si(A, B, 1)
+#define __builtin_ia32_vpshld_v16si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v16si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8di(A, B, C) __builtin_ia32_vpshld_v8di(A, B, 1)
+#define __builtin_ia32_vpshld_v8di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8di_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v16hi(A, B, C) __builtin_ia32_vpshld_v16hi(A, B, 1)
+#define __builtin_ia32_vpshld_v16hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v16hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8si(A, B, C) __builtin_ia32_vpshld_v8si(A, B, 1)
+#define __builtin_ia32_vpshld_v8si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v4di(A, B, C) __builtin_ia32_vpshld_v4di(A, B, 1)
+#define __builtin_ia32_vpshld_v4di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v4di_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8hi(A, B, C) __builtin_ia32_vpshld_v8hi(A, B, 1)
+#define __builtin_ia32_vpshld_v8hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v4si(A, B, C) __builtin_ia32_vpshld_v4si(A, B, 1)
+#define __builtin_ia32_vpshld_v4si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v4si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v2di(A, B, C) __builtin_ia32_vpshld_v2di(A, B, 1)
+#define __builtin_ia32_vpshld_v2di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v2di_mask(A, B, 1, D, E)
+
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 3a90e54..ac55847 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -619,6 +619,26 @@
#define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D)
#define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D)
+/* avx512vbmi2intrin.h */
+#define __builtin_ia32_vpshld_v32hi(A, B, C) __builtin_ia32_vpshld_v32hi(A, B, 1)
+#define __builtin_ia32_vpshld_v32hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v32hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v16si(A, B, C) __builtin_ia32_vpshld_v16si(A, B, 1)
+#define __builtin_ia32_vpshld_v16si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v16si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8di(A, B, C) __builtin_ia32_vpshld_v8di(A, B, 1)
+#define __builtin_ia32_vpshld_v8di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8di_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v16hi(A, B, C) __builtin_ia32_vpshld_v16hi(A, B, 1)
+#define __builtin_ia32_vpshld_v16hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v16hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8si(A, B, C) __builtin_ia32_vpshld_v8si(A, B, 1)
+#define __builtin_ia32_vpshld_v8si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v4di(A, B, C) __builtin_ia32_vpshld_v4di(A, B, 1)
+#define __builtin_ia32_vpshld_v4di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v4di_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v8hi(A, B, C) __builtin_ia32_vpshld_v8hi(A, B, 1)
+#define __builtin_ia32_vpshld_v8hi_mask(A, B, C, D, E) __builtin_ia32_vpshld_v8hi_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v4si(A, B, C) __builtin_ia32_vpshld_v4si(A, B, 1)
+#define __builtin_ia32_vpshld_v4si_mask(A, B, C, D, E) __builtin_ia32_vpshld_v4si_mask(A, B, 1, D, E)
+#define __builtin_ia32_vpshld_v2di(A, B, C) __builtin_ia32_vpshld_v2di(A, B, 1)
+#define __builtin_ia32_vpshld_v2di_mask(A, B, C, D, E) __builtin_ia32_vpshld_v2di_mask(A, B, 1, D, E)
+
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid")
#include <x86intrin.h>
--
2.5.5
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH][i386,AVX] Enable VBMI2 support [4/7]
2017-10-24 9:10 [PATCH][i386,AVX] Enable VBMI2 support [4/7] Koval, Julia
@ 2017-11-28 18:06 ` Kirill Yukhin
0 siblings, 0 replies; 2+ messages in thread
From: Kirill Yukhin @ 2017-11-28 18:06 UTC (permalink / raw)
To: Koval, Julia; +Cc: GCC Patches
Hello Julia,
On 24 Oct 09:08, Koval, Julia wrote:
> Hi,
> This patch enables VPSHLD instruction. The doc for isaset and instruction: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> Ok for trunk?
You patch is OK for trunk. I've checked it in.
--
Thanks, K
^ permalink raw reply [flat|nested] 2+ messages in thread
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2017-10-24 9:10 [PATCH][i386,AVX] Enable VBMI2 support [4/7] Koval, Julia
2017-11-28 18:06 ` Kirill Yukhin
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